| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1928 from YosysHQ/eddie/design_delete | Eddie Hung | 2020-04-16 | 1 | -1/+21 |
| |\ | | | | | kernel: add design -delete option | ||||
| | * | kernel: add design -delete option | Eddie Hung | 2020-04-16 | 1 | -1/+21 |
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| * | | design: do not delete when iterating over Design::modules() directly | Eddie Hung | 2020-04-14 | 1 | -1/+1 |
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| * | Merge pull request #1859 from boqwxp/design_duplicate | whitequark | 2020-04-06 | 1 | -2/+13 |
| |\ | | | | | Add `-push-copy` option to the `design` command. | ||||
| | * | Rename `-duplicate` to `-push-copy`. | Alberto Gonzalez | 2020-04-04 | 1 | -6/+6 |
| | | | | | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org> | ||||
| | * | Add `-duplicate` option to the `design` command. | Alberto Gonzalez | 2020-04-03 | 1 | -2/+13 |
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| * | | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -3/+3 |
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| * | Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design | Eddie Hung | 2020-03-30 | 1 | -31/+33 |
| |\ | | | | | Clean up pseudo-private member usage in `passes/cmds/design.cc`. | ||||
| | * | Replace `RTLIL::id2cstr()` with `log_id()`. | Alberto Gonzalez | 2020-03-30 | 1 | -1/+1 |
| | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | ||||
| | * | Clean up pseudo-private member usage in `passes/cmds/design.cc`. | Alberto Gonzalez | 2020-03-28 | 1 | -31/+33 |
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| * | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 1 | -1/+2 |
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly. | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -3/+3 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Add "design -import" | Clifford Wolf | 2017-06-30 | 1 | -3/+94 |
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| * | Added "design -reset-vlog" | Clifford Wolf | 2016-11-30 | 1 | -7/+32 |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
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| * | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
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| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -2/+3 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -0/+4 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -11/+11 |
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| * | Added "design -push" and "design -pop" | Clifford Wolf | 2014-02-20 | 1 | -8/+45 |
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| * | Fixed use of "cmd_error" in passes/cmds/design.cc | Clifford Wolf | 2014-02-07 | 1 | -2/+2 |
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| * | Added design -stash/-copy-from/-copy-to | Clifford Wolf | 2014-02-06 | 1 | -13/+99 |
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| * | Added "design" command (-reset, -save, -load) | Clifford Wolf | 2013-07-27 | 1 | -0/+128 |
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index : iCE40/yosys | |
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