| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 1 | -1/+1 |
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| * | Add clean_zerowidth pass, use it for Verilog output. | Marcelina Kościelnicka | 2021-12-12 | 1 | -0/+210 |
| This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103. | |||||
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index : iCE40/yosys | |
| [no description] |
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