index
:
iCE40/yosys
master
clone of https://github.com/YosysHQ/yosys
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
manual
Commit message (
Collapse
)
Author
Age
Files
Lines
...
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
5
-13
/
+13
|
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
3
-8
/
+2
|
*
Removed references to yosys-svgviewer from docs
Clifford Wolf
2014-09-02
2
-21
/
+10
|
*
Added $alu cell type
Clifford Wolf
2014-08-30
1
-0
/
+4
|
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵
Clifford Wolf
2014-08-16
1
-0
/
+4
|
|
|
|
$_OAI4_
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
4
-6
/
+6
|
*
Removed old doc references to $safe_pmux
Clifford Wolf
2014-08-15
2
-5
/
+1
|
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
1
-1
/
+1
|
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
2
-9
/
+3
|
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
2
-24
/
+17
|
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
1
-1
/
+1
|
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
2
-5
/
+5
|
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
2
-2
/
+2
|
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
2
-4
/
+4
|
*
generated by
cgit v1.2.3
(
git 2.25.1
) at 2025-09-03 12:12:28 +0000