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* Add flooring division operatorXiretza2020-05-281-1/+1
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-1/+1
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-2/+2
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* Fixed trailing whitespacesClifford Wolf2015-07-021-1/+1
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* Various presentation fixesClifford Wolf2015-02-091-7/+14
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* Various documentation updatesClifford Wolf2014-11-081-37/+42
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* Removed $bu0 cell typeClifford Wolf2014-09-041-1/+1
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
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