iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
\| \| \| \| \| \| \| \|	s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
*	Respect \A_SIGNED for $shift	Xiretza	2020-08-18	1	-40/+20
\| \| \| \| \| \|	This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
*	Add flooring division operator	Xiretza	2020-05-28	1	-0/+22
\| \| \| \| \| \| \| \| \| \|	The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
*	Add flooring modulo operator	Xiretza	2020-05-28	1	-0/+25
\| \| \| \| \| \| \| \| \| \| \|	The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
*	Fix mingw compile issue (2nd attempt)	Clifford Wolf	2017-02-23	1	-2/+2
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*	Fix mingw compile issue (maybe.. I can't test it)	Clifford Wolf	2017-02-23	1	-2/+2
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-10/+10
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
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*	Fixed const2big performance bug	Clifford Wolf	2015-04-09	1	-14/+21
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-21/+0
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*	Using $pos models for $bu0	Clifford Wolf	2014-09-03	1	-1/+1
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*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02	1	-3/+2
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*	Fixed return size of const_*() eval functions	Clifford Wolf	2014-08-31	1	-1/+5
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+5
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-5/+38
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
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*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06	1	-2/+2
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-0/+8
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-0/+29
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*	More undef-propagation related fixes	Clifford Wolf	2013-11-08	1	-0/+5
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*	Removed debug log from const_pow()	Clifford Wolf	2013-11-08	1	-1/+0
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*	Fixed handling of power operator	Clifford Wolf	2013-11-07	1	-9/+41
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*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07	1	-8/+17
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*	Improved undef handling in == and != for ConstEval	Clifford Wolf	2013-11-06	1	-11/+25
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-64/+97
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*	Fixed handling of undef values in POS cells in ConstEval	Clifford Wolf	2013-11-06	1	-3/+1
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*	Fixed sign handling in const eval of sshl and sshr	Clifford Wolf	2013-11-05	1	-2/+6
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*	Fixed signed div/mod in const eval (rounding and stuff)	Clifford Wolf	2013-08-15	1	-2/+8
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*	Added eval -brute_force_equiv_checker_x mode	Clifford Wolf	2013-08-15	1	-4/+10
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*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14	1	-26/+53
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+392