| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | Same for ascii AIGERs too | Eddie Hung | 2019-02-19 | 1 | -6/+13 | |
| | | | | ||||||
| * | | | read_aiger to cope with non-unique POs | Eddie Hung | 2019-02-19 | 1 | -6/+13 | |
| | | | | ||||||
| * | | | read_aiger to create sane $lut names, and rename when renaming driving wire | Eddie Hung | 2019-02-19 | 1 | -2/+11 | |
| | | | | ||||||
| * | | | Add comment | Eddie Hung | 2019-02-19 | 1 | -1/+2 | |
| | | | | ||||||
| * | | | Get rid of boost dep, fix the FIXMEs for Win32? | Eddie Hung | 2019-02-19 | 1 | -14/+14 | |
| | | | | ||||||
| * | | | In read_xaiger, do not construct ConstEval for every LUT | Eddie Hung | 2019-02-16 | 1 | -1/+1 | |
| | | | | ||||||
| * | | | read_aiger to ignore output = input of same wire; also create new output for ↵ | Eddie Hung | 2019-02-16 | 1 | -2/+16 | |
| | | | | | | | | | | | | | different wire | |||||
| * | | | read_aiger to disable log_debug | Eddie Hung | 2019-02-16 | 1 | -1/+2 | |
| | | | | ||||||
| * | | | read_xaiger() to use f.read() not readsome() | Eddie Hung | 2019-02-16 | 1 | -1/+2 | |
| | | | | ||||||
| * | | | read_aiger() to cope with constant outputs, mixed wideports, do cleaning | Eddie Hung | 2019-02-16 | 1 | -8/+130 | |
| | | | | ||||||
| * | | | read_aiger with more asserts, and call clean | Eddie Hung | 2019-02-15 | 1 | -4/+11 | |
| | | | | ||||||
| * | | | Leave FIXME for clean | Eddie Hung | 2019-02-13 | 1 | -3/+3 | |
| | | | | ||||||
| * | | | Use module->addLut() | Eddie Hung | 2019-02-13 | 1 | -5/+1 | |
| | | | | ||||||
| * | | | Use ConstEval to compute LUT masks | Eddie Hung | 2019-02-13 | 2 | -63/+69 | |
| | | | | ||||||
| * | | | Merge remote-tracking branch 'origin/read_aiger' into xaig | Eddie Hung | 2019-02-13 | 1 | -10/+3 | |
| |\| | | ||||||
| | * | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 | |
| | |\ \ | ||||||
| | | * | | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
| | | | | | ||||||
| | | * | | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 | |
| | | | | | ||||||
| | | * | | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
| | | | | | ||||||
| | * | | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 | |
| | |/ / | ||||||
| * | | | Merge https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-13 | 1 | -5/+4 | |
| |\ \ \ | | |/ | |/| | ||||||
| | * | | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add support for read_aiger -wideports | Eddie Hung | 2019-02-12 | 2 | -6/+15 | |
| | | | | ||||||
| * | | | Add support for read_aiger -map | Eddie Hung | 2019-02-12 | 2 | -4/+82 | |
| | | | | ||||||
| * | | | Parse 'm' in xaiger | Eddie Hung | 2019-02-12 | 1 | -20/+57 | |
| | | | | ||||||
| * | | | Add read_xaiger | Eddie Hung | 2019-02-11 | 2 | -27/+108 | |
| | |/ |/| | ||||||
| * | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | ||||||
| * | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 | |
| | | | ||||||
| * | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 | |
| | | | ||||||
| * | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | ||||||
| * | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 | |
| | | | ||||||
| * | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 | |
| | | | ||||||
| * | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 | |
| | | | ||||||
| * | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 | |
| | | | ||||||
| * | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 | |
| | | | ||||||
| * | | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 | |
| | | | ||||||
| * | | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | ||||||
| * | | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 | |
| | | | ||||||
| * | | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 | |
| | | | ||||||
| * | | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 | |
| | | | ||||||
| * | | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 | |
| | | | ||||||
| * | | Stub for binary AIGER | Eddie Hung | 2019-02-08 | 1 | -3/+8 | |
| | | | ||||||
| * | | Refactor | Eddie Hung | 2019-02-06 | 1 | -1/+8 | |
| | | | ||||||
| * | | WIP | Eddie Hung | 2019-02-06 | 3 | -0/+247 | |
| |/ | ||||||
| * | Bugfix in Verilog string handling | Clifford Wolf | 2019-01-05 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Remove -m32 Verific eval lib build instructions | Clifford Wolf | 2019-01-04 | 1 | -29/+0 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve VerificImporter support for writes to asymmetric memories | Clifford Wolf | 2019-01-02 | 1 | -22/+35 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix VerificImporter asymmetric memories error message | Clifford Wolf | 2019-01-02 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 5 | -11/+11 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | Add "read_ilang -[no]overwrite" | Clifford Wolf | 2018-12-23 | 3 | -4/+54 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |