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* read_aiger to create sane $lut names, and rename when renaming driving wireEddie Hung2019-02-191-2/+11
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* Add commentEddie Hung2019-02-191-1/+2
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* Get rid of boost dep, fix the FIXMEs for Win32?Eddie Hung2019-02-191-14/+14
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* In read_xaiger, do not construct ConstEval for every LUTEddie Hung2019-02-161-1/+1
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* read_aiger to ignore output = input of same wire; also create new output for ↵Eddie Hung2019-02-161-2/+16
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* read_aiger to disable log_debugEddie Hung2019-02-161-1/+2
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* read_xaiger() to use f.read() not readsome()Eddie Hung2019-02-161-1/+2
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* read_aiger() to cope with constant outputs, mixed wideports, do cleaningEddie Hung2019-02-161-8/+130
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* read_aiger with more asserts, and call cleanEddie Hung2019-02-151-4/+11
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* Leave FIXME for cleanEddie Hung2019-02-131-3/+3
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* Use module->addLut()Eddie Hung2019-02-131-5/+1
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* Use ConstEval to compute LUT masksEddie Hung2019-02-132-63/+69
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* Merge remote-tracking branch 'origin/read_aiger' into xaigEddie Hung2019-02-131-10/+3
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| * Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aigerEddie Hung2019-02-121-3/+1
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| | * Do not break for constraintsEddie Hung2019-02-111-1/+0
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| | * No increment line_count for binary ANDsEddie Hung2019-02-111-1/+1
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| | * Do not ignore newline after AND in binary AIGEddie Hung2019-02-111-1/+0
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| * | Use module->add{Not,And}Gate() functionsEddie Hung2019-02-121-8/+2
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* | Merge https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-131-5/+4
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| * | Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add support for read_aiger -wideportsEddie Hung2019-02-122-6/+15
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* | | Add support for read_aiger -mapEddie Hung2019-02-122-4/+82
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* | | Parse 'm' in xaigerEddie Hung2019-02-121-20/+57
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* | | Add read_xaigerEddie Hung2019-02-112-27/+108
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* | addDff -> addDffGate as per @daveshah1Eddie Hung2019-02-081-1/+1
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* | Fix tabulationEddie Hung2019-02-081-28/+28
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* | -module_name arg to go before -clk_nameEddie Hung2019-02-081-7/+7
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* | Add missing "[options]" to read_blif helpEddie Hung2019-02-081-1/+1
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* | Allow module name to be determined by argument tooEddie Hung2019-02-082-14/+44
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* | Refactor into AigerReader classEddie Hung2019-02-082-79/+92
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* | Parse binary AIG filesEddie Hung2019-02-081-49/+164
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* | Refactor to parse_aiger_header()Eddie Hung2019-02-081-26/+32
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* | Add commentEddie Hung2019-02-081-0/+1
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* | Handle reset logic in latchesEddie Hung2019-02-081-2/+17
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* | Change literal vars from int to unsignedEddie Hung2019-02-081-1/+1
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* | Create clk outside of latch loopEddie Hung2019-02-081-7/+9
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* | Handle latch symbols tooEddie Hung2019-02-081-3/+1
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* | Remove return after log_errorEddie Hung2019-02-081-27/+9
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* | Add support for symbol tablesEddie Hung2019-02-081-1/+49
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* | Stub for binary AIGEREddie Hung2019-02-081-3/+8
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* | RefactorEddie Hung2019-02-061-1/+8
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* | WIPEddie Hung2019-02-063-0/+247
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* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve VerificImporter support for writes to asymmetric memoriesClifford Wolf2019-01-021-22/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix VerificImporter asymmetric memories error messageClifford Wolf2019-01-021-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-025-11/+11
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve src tagging (using names and attrs) of cells and wires in verific ↵Clifford Wolf2018-12-182-99/+160
| | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at>
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