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* | sv: fix up end label checkingZachary Snow2021-06-161-7/+18
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* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-0925-25/+25
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0825-25/+25
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-083-13/+30
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-081-5/+42
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* sv: support tasks and functions within packagesZachary Snow2021-06-013-2/+22
* verilog: fix case expression sign and width handlingZachary Snow2021-05-253-12/+49
* sv: support remaining assignment operatorsZachary Snow2021-05-252-42/+41
* Change the type of current_module to ModuleRupert Swarbrick2021-05-132-24/+26
* Use range-based for loop in AST::processRupert Swarbrick2021-05-131-21/+21
* sv: check validity of package end labelZachary Snow2021-05-101-0/+2
* blif: Use library cells' start_offset and upto for wideports.Marcelina Kościelnicka2021-05-081-10/+27
* Remove duplicates from conns array in JSON front-end, fixes #2736Claire Xenia Wolf2021-04-261-0/+4
* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
* preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
* verilog: check entire user type stack for type definitionXiretza2021-03-211-6/+12
* sv: allow typenames as function return typesZachary Snow2021-03-191-0/+6
* verilog: rebuild user_type_stack from globals before parsing fileXiretza2021-03-181-5/+21
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-2/+25
* sv: carry over global typedefs from previous filesZachary Snow2021-03-171-2/+5
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-4/+15
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-4/+8
* json: Add support for memories.Marcelina Kościelnicka2021-03-151-0/+46
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-122-1/+1
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+2
* Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
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| * Fix param without default log lineZachary Snow2021-03-071-1/+1
* | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-084-29/+89
* | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-082-1/+19
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* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-072-5/+48
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| * sv: support for parameters without default valuesZachary Snow2021-03-022-5/+48
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-071-0/+6
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| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-041-0/+6
* | | sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-062-1/+23
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* / Update READMEClaire Xen2021-03-041-4/+4
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* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-011-2/+3
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-011-11/+38
* Merge pull request #2523 from tomverbeure/define_synthesisClaire Xen2021-03-011-3/+12
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| * Fix indents.Tom Verbeure2021-01-041-2/+2
| * Add -nosynthesis flag for read_verilog command.Tom Verbeure2021-01-041-3/+12
* | Merge pull request #2615 from zachjs/genrtlil-conflictwhitequark2021-03-011-12/+37
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| * | genrtlil: improve name conflict error messagingZachary Snow2021-02-261-12/+37
* | | sv: extended support for integer typesZachary Snow2021-02-282-39/+70
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