iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| \| * \| \| \| \|	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968	Clifford Wolf	2019-05-06	5	-4/+15
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\| \| * \| \| \| \| \|	Re-enable "final loop assignment" feature	Clifford Wolf	2019-05-01	1	-2/+0
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\| * \| \| \| \| \|	Merge pull request #871 from YosysHQ/verific_import	Clifford Wolf	2019-05-06	2	-26/+71
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\| \| * \| \| \| \|	For hier_tree::Elaborate() also include SV root modules (bind)	Eddie Hung	2019-05-03	1	-23/+36
\| \| * \| \| \| \|	Fix verific_parameters construction, use attribute to mark top netlists	Eddie Hung	2019-05-03	2	-8/+12
\| \| * \| \| \| \|	WIP -chparam support for hierarchy when verific	Eddie Hung	2019-05-03	2	-12/+17
\| \| * \| \| \| \|	verific_import() changes to avoid ElaborateAll()	Eddie Hung	2019-05-03	1	-15/+38
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\| * \| \| \| \|	Fix the other bison warning in ilang_parser.y	Clifford Wolf	2019-05-06	1	-1/+1
\| * \| \| \| \|	verilog_parser: Fix Bison warning	Ben Widawsky	2019-05-05	1	-1/+1
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\| * \| \| \|	Merge pull request #988 from YosysHQ/clifford/fix987	Clifford Wolf	2019-05-04	2	-1/+5
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\| \| * \| \| \|	Add approximate support for SV "var" keyword, fixes #987	Clifford Wolf	2019-05-04	2	-1/+5
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\| * / / /	Add support for SVA "final" keyword	Clifford Wolf	2019-05-04	2	-1/+5
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\| * \| \|	Add splitcmplxassign test case and silence splitcmplxassign warning	Clifford Wolf	2019-05-01	1	-0/+1
\| * \| \|	Fix width detection of memory access with bit slice, fixes #974	Clifford Wolf	2019-05-01	1	-0/+2
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\| * \|	Disabled "final loop assignment" feature	Clifford Wolf	2019-04-30	1	-0/+2
\| * \|	Merge pull request #972 from YosysHQ/clifford/fix968	Clifford Wolf	2019-04-30	1	-0/+7
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\| \| * \|	Add final loop variable assignment when unrolling for-loops, fixes #968	Clifford Wolf	2019-04-30	1	-0/+7
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\| * /	Include filename in "Executing Verilog-2005 frontend" message, fixes #959	Clifford Wolf	2019-04-30	1	-2/+2
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* \|	Move clean from aigerparse to abc9	Eddie Hung	2019-04-23	1	-2/+0
* \|	Tidy up	Eddie Hung	2019-04-22	1	-1/+1
* \|	Revert "Temporarily remove 'r' extension"	Eddie Hung	2019-04-22	1	-0/+18
* \|	Temporarily remove 'r' extension	Eddie Hung	2019-04-22	1	-18/+0
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-22	2	-7/+38
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\| *	Merge pull request #952 from YosysHQ/clifford/fix370	Clifford Wolf	2019-04-22	1	-3/+18
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\| \| *	Determine correct signedness and expression width in for loop unrolling, fixe...	Clifford Wolf	2019-04-22	1	-3/+18
\| * \|	Add log_debug() framework	Clifford Wolf	2019-04-22	1	-2/+0
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\| *	Merge pull request #909 from zachjs/master	Clifford Wolf	2019-04-22	1	-1/+20
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\| \| *	support repeat loops with constant repeat counts outside of constant functions	Zachary Snow	2019-04-09	1	-1/+20
* \| \|	Merge remote-tracking branch 'origin/clifford/libwb' into xaig	Eddie Hung	2019-04-21	5	-35/+111
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\| * \|	Add "noblackbox" attribute	Clifford Wolf	2019-04-21	1	-17/+27
\| * \|	New behavior for front-end handling of whiteboxes	Clifford Wolf	2019-04-20	5	-34/+100
* \| \|	read_aiger to parse 'r' extension	Eddie Hung	2019-04-18	1	-0/+18
* \| \|	Merge remote-tracking branch 'origin/clifford/whitebox' into xaig	Eddie Hung	2019-04-18	5	-11/+42
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\| * \|	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	5	-11/+42
* \| \|	Ignore a/i/o/h XAIGER extensions	Eddie Hung	2019-04-17	1	-0/+7
* \| \|	Forgot backslashes	Eddie Hung	2019-04-12	1	-1/+1
* \| \|	Handle __dummy_o__ and __const[01]__ in read_aiger not abc	Eddie Hung	2019-04-12	1	-0/+4
* \| \|	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	Eddie Hung	2019-04-12	1	-12/+32
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\| * \| \|	Fix inout handling for -map option	Eddie Hung	2019-04-12	1	-10/+30
* \| \| \|	Also cope with duplicated CIs	Eddie Hung	2019-04-12	1	-5/+23
* \| \| \|	Cope with an output having same name as an input (i.e. CO)	Eddie Hung	2019-04-12	1	-5/+23
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* \| \|	parse_aiger() to rename all $lut cells after "clean"	Eddie Hung	2019-04-10	1	-24/+21
* \| \|	Fix spacing	Eddie Hung	2019-04-08	1	-29/+29
* \| \|	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	15	-142/+500
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\| * \|	Add "read_ilang -lib"	Clifford Wolf	2019-04-05	3	-3/+14
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\| *	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906	Clifford Wolf	2019-03-29	1	-0/+2
\| *	Add "read -verific" and "read -noverific"	Clifford Wolf	2019-03-27	1	-6/+28
\| *	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	1	-15/+71
\| *	Fix mem2reg handling of memories with upto data ports, fixes #888	Clifford Wolf	2019-03-21	1	-1/+10
\| *	Improve "read_verilog -dump_vlog[12]" handling of upto ranges	Clifford Wolf	2019-03-21	1	-3/+6