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* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-4/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-4/+8
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* json: Add support for memories.Marcelina Kościelnicka2021-03-151-0/+46
| | | | | | | | | | | | | | Previously, memories were silently discarded by the JSON backend, making round-tripping modules with them crash. Since there are already some users using JSON to implement custom external passes that use memories (and infer width/size from memory ports), let's fix this by just making JSON backend and frontend support memories as first-class objects. Processes are still not supported, and will now cause a hard error. Fixes #1908.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-122-1/+1
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+2
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
|\ | | | | Fix param without default log line
| * Fix param without default log lineZachary Snow2021-03-071-1/+1
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* | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-084-29/+89
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* | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-082-1/+19
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* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-072-5/+48
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-022-5/+48
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-071-0/+6
|\ \ | | | | | | verilog: impose limit on maximum expression width
| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-041-0/+6
| | | | | | | | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* | | sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-062-1/+23
|/ / | | | | | | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* / Update READMEClaire Xen2021-03-041-4/+4
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* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-011-2/+3
| | | | | | Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-011-11/+38
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* Merge pull request #2523 from tomverbeure/define_synthesisClaire Xen2021-03-011-3/+12
|\ | | | | Add -nosynthesis flag for read_verilog command
| * Fix indents.Tom Verbeure2021-01-041-2/+2
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| * Add -nosynthesis flag for read_verilog command.Tom Verbeure2021-01-041-3/+12
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* | Merge pull request #2615 from zachjs/genrtlil-conflictwhitequark2021-03-011-12/+37
|\ \ | | | | | | genrtlil: improve name conflict error messaging
| * | genrtlil: improve name conflict error messagingZachary Snow2021-02-261-12/+37
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* | | sv: extended support for integer typesZachary Snow2021-02-282-39/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* | | Implement $countones, $isunknown and $onehot{,0}Michael Singer2021-02-261-0/+28
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* | | Implement $countbits functionMichael Singer2021-02-261-0/+59
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* | | Extend simplify() recursion warningZachary Snow2021-02-261-1/+1
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* | | Merge pull request #2554 from hzeller/masterwhitequark2021-02-251-6/+17
|\ \ \ | | | | | | | | Fix digit-formatting calculation for small numbers.
| * | | Provide an integer implementation of decimal_digits().Henner Zeller2021-02-011-2/+9
| | | | | | | | | | | | | | | | Signed-off-by: Henner Zeller <h.zeller@acm.org>
| * | | Fix digit-formatting calculation for small numbers.Henner Zeller2021-01-211-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling log10() on zero causes a non-sensical value to be calculated. On some compile options, I've observed yosys crashing with an illegal instruction (SIGILL). To make it safe, fix the calculation to do a range check; wrap it a decimal_digits() function, and use it where the previous ceil(log10(n)) call was used. As a side, it also improves readability. Signed-off-by: Henner Zeller <h.zeller@acm.org>
* | | | Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-252-15/+16
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | Basically: - priority converts to (* full_case *) - unique0 converts to (* parallel_case *) - unique converts to (* parallel_case, full_case *) Fixes #2596.
* | | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and ↵TimRudy2021-02-241-2/+7
| | | | | | | | | | | | turn-off (#2566)
* | | frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-234-57/+71
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* | | Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-232-10/+30
|\ \ \ | | | | | | | | verilog: fix sizing of constant args for tasks/functions
| * | | verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-212-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | | | frontend: json: parse negative valuesKarol Gugala2021-02-231-2/+10
| | | | | | | | | | | | | | | | Signed-off-by: Karol Gugala <kgugala@antmicro.com>
* | | | Merge pull request #2586 from zachjs/tern-recursewhitequark2021-02-213-19/+119
|\ \ \ \ | | | | | | | | | | verilog: support recursive functions using ternary expressions
| * | | | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-123-19/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* | | | | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-191-1/+10
| |/ / / |/| | | | | | | | | | | | | | | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* | | | Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
|\ \ \ \ | |/ / / |/| | | Accept disable case for SVA liveness properties.
| * | | Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
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* | | | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
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* | | | Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-112-72/+82
|\ \ \ \ | | | | | | | | | | verilog: refactored constant function evaluation
| * | | | verilog: refactored constant function evaluationZachary Snow2021-02-042-72/+82
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* | | | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
|\ \ \ \ | | | | | | | | | | verlog: allow shadowing module ports within generate blocks
| * | | | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | | | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
|/ / / / | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-051-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* | | | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
|/ / / | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-043-148/+169
|\ \ \ | | | | | | | | verilog: significant block scoping improvements
| * | | verilog: significant block scoping improvementsZachary Snow2021-01-313-148/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 02:20:51 +0000