Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Adding error message for when size (width) of number literal is zero | Diego H | 2020-03-30 | 1 | -0/+4 |
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* | Merge pull request #1783 from boqwxp/astcc_cleanup | Eddie Hung | 2020-03-30 | 1 | -13/+20 |
|\ | | | | | Clean up pseudo-private member usage in `frontends/ast/ast.cc`. | ||||
| * | Add explanatory comment about inefficient wire removal and remove ↵ | Alberto Gonzalez | 2020-03-30 | 1 | -4/+8 |
| | | | | | | | | | | | | superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | ||||
| * | Revert over-aggressive change to a more modest cleanup. | Alberto Gonzalez | 2020-03-27 | 1 | -2/+3 |
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| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`. | Alberto Gonzalez | 2020-03-19 | 1 | -11/+13 |
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* | | Merge pull request #1811 from PeterCrozier/typedef_scope | N. Engelhardt | 2020-03-30 | 4 | -41/+81 |
|\ \ | | | | | | | Support module/package/interface/block scope for typedef names. | ||||
| * | | Inline productions to follow house style. | Peter Crozier | 2020-03-27 | 1 | -33/+29 |
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| * | | Error duplicate declarations of a typedef name in the same scope. | Peter Crozier | 2020-03-24 | 2 | -3/+11 |
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| * | | Support module/package/interface/block scope for typedef names. | Peter Crozier | 2020-03-23 | 4 | -20/+56 |
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* | | | Merge pull request #1778 from rswarbrick/sv-defines | N. Engelhardt | 2020-03-30 | 4 | -149/+578 |
|\ \ \ | | | | | | | | | Add support for SystemVerilog-style `define to Verilog frontend | ||||
| * | | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 4 | -149/+578 |
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly. | ||||
* | | | Merge pull request #1607 from whitequark/simplify-simplify-meminit | Claire Wolf | 2020-03-27 | 1 | -63/+82 |
|\ \ \ | |/ / |/| | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT | ||||
| * | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. | whitequark | 2020-02-07 | 1 | -65/+84 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`. | ||||
* | | | Simplify was not being called for packages. Broke typedef enums. | Peter Crozier | 2020-03-22 | 1 | -5/+8 |
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* | | | Build pkg_user_types before parsing in case of changes in the design. | Peter Crozier | 2020-03-22 | 1 | -6/+3 |
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* | | | Clear pkg_user_types if no packages following a 'design -reset-vlog'. | Peter | 2020-03-22 | 2 | -0/+5 |
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* | | | Parser changes to support typedef. | Peter | 2020-03-22 | 4 | -10/+88 |
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* | | | Merge pull request #1788 from YosysHQ/eddie/fix_ndebug | Eddie Hung | 2020-03-19 | 2 | -2/+2 |
|\ \ \ | | | | | | | | | Fix NDEBUG warnings | ||||
| * | | | Fix NDEBUG warnings | Eddie Hung | 2020-03-19 | 2 | -2/+2 |
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* | | | | Merge pull request #1787 from YosysHQ/mmicko/lexer_deps | Miodrag Milanović | 2020-03-19 | 1 | -1/+1 |
|\ \ \ \ | |/ / / |/| | | | Add dependency to verilog_lexer.cc | ||||
| * | | | Add one mode dependency | Miodrag Milanovic | 2020-03-19 | 1 | -1/+1 |
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* | | | Merge pull request #1775 from huaixv/asserts_locations | N. Engelhardt | 2020-03-19 | 2 | -7/+31 |
|\ \ \ | |/ / |/| | | Add precise locations for asserts | ||||
| * | | Add precise locations for asserts | huaixv | 2020-03-19 | 2 | -7/+31 |
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* | | | Add AST node source location information in a couple more parser rules. | Alberto Gonzalez | 2020-03-17 | 1 | -0/+2 |
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* | | Merge pull request #1759 from zeldin/constant_with_comment_redux | Miodrag Milanović | 2020-03-14 | 2 | -19/+43 |
|\ \ | | | | | | | refixed parsing of constant with comment between size and value | ||||
| * | | refixed parsing of constant with comment between size and value | Marcus Comstedt | 2020-03-11 | 2 | -19/+43 |
| | | | | | | | | | | | | | | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace. | ||||
* | | | Merge pull request #1754 from boqwxp/precise_locations | Miodrag Milanović | 2020-03-14 | 1 | -2/+53 |
|\ \ \ | | | | | | | | | Set AST node source location in more parser rules. | ||||
| * | | | verilog: also set location for simple_behavioral_stmt | Eddie Hung | 2020-03-10 | 1 | -0/+4 |
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| * | | | Set AST source locations in more parser rules. | Alberto Gonzalez | 2020-03-10 | 1 | -2/+49 |
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* / / | Fix compilation for emcc | jiegec | 2020-03-11 | 1 | -1/+2 |
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* | | Fix partsel expr bit width handling and add test case | Claire Wolf | 2020-03-08 | 1 | -4/+6 |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | Fix bison warning for "pure-parser" option | Claire Wolf | 2020-03-03 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 8 | -299/+384 |
|\ \ | | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. | ||||
| * | | Closes #1717. Add more precise Verilog source location information to AST ↵ | Alberto Gonzalez | 2020-02-23 | 8 | -299/+384 |
| | | | | | | | | | | | | and RTLIL nodes. | ||||
* | | | Merge pull request #1681 from YosysHQ/eddie/fix1663 | Claire Wolf | 2020-03-03 | 1 | -15/+13 |
|\ \ \ | | | | | | | | | verilog: instead of modifying localparam size, extend init constant expr | ||||
| * | | | verilog: instead of modifying localparam size, extend init constant expr | Eddie Hung | 2020-02-05 | 1 | -15/+13 |
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* | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specify | Eddie Hung | 2020-03-02 | 2 | -12/+20 |
|\ \ \ | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries | ||||
| * | | | ast: quiet down when deriving blackbox modules | Eddie Hung | 2020-02-27 | 2 | -12/+20 |
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* | | | ast: fixes #1710; do not generate RTLIL for unreachable ternary | Eddie Hung | 2020-02-27 | 1 | -9/+22 |
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* | | | Comment out log() | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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* | | Merge pull request #1703 from YosysHQ/eddie/specify_improve | Eddie Hung | 2020-02-21 | 3 | -36/+92 |
|\ \ | | | | | | | Improve specify parser | ||||
| * | | verilog: add support for more delays than just rise/fall | Eddie Hung | 2020-02-19 | 1 | -1/+40 |
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| * | | verilog: ignore ranges too without -specify | Eddie Hung | 2020-02-13 | 1 | -1/+2 |
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| * | | verilog: improve specify support when not in -specify mode | Eddie Hung | 2020-02-13 | 1 | -13/+7 |
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| * | | verilog: ignore '&&&' when not in -specify mode | Eddie Hung | 2020-02-13 | 2 | -5/+6 |
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| * | | specify: system timing checks to accept min:typ:max triple | Eddie Hung | 2020-02-13 | 1 | -12/+29 |
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| * | | verilog: fix $specify3 check | Eddie Hung | 2020-02-13 | 1 | -7/+11 |
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* | | | Merge pull request #1642 from jjj11x/jjj11x/sv-enum | Claire Wolf | 2020-02-20 | 5 | -18/+325 |
|\ \ \ | |/ / |/| | | Enum support | ||||
| * | | remove unnecessary blank line | Jeff Wang | 2020-02-17 | 1 | -2/+1 |
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| * | | add attributes for enumerated values in ilang | Jeff Wang | 2020-02-17 | 3 | -2/+76 |
| | | | | | | | | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files |