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* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-031-0/+11
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| * Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵Clifford Wolf2019-05-301-0/+3
| | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Assert that box_unique_id is indeed uniqueEddie Hung2019-06-031-2/+3
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* | Skip internal modules when generating box_unique_idEddie Hung2019-06-031-0/+1
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* | parse_xaiger to cope with flopsEddie Hung2019-05-312-83/+123
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* | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-0/+18
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| * | Move clean from aigerparse to abc9Eddie Hung2019-04-231-2/+0
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| * | Tidy upEddie Hung2019-04-221-1/+1
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| * | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-221-0/+18
| | | | | | | | | | | | This reverts commit eaf3c247729365cec776e147f380ce59f7dccd4d.
* | | read_xaiger() to name box signalsEddie Hung2019-05-301-4/+8
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* | | Remove whitespaceEddie Hung2019-05-301-1/+0
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* | | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-301-0/+38
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-286-15/+61
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| * | Merge branch 'master' into wandworStefan Biereigel2019-05-275-14/+47
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| | * \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
| | |\ \ | | | | | | | | | | Give error instead of asserting for invalid range, fixes #947
| | | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
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| | * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-275-13/+45
| | |/ / | | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
| * | | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
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| * | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
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| * | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
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| * | | fix indentation across filesStefan Biereigel2019-05-234-63/+83
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| * | | implementation for assignments workingStefan Biereigel2019-05-233-14/+83
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| * | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-233-2/+10
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* | | read_aiger to only clean own designEddie Hung2019-05-281-0/+6
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* | | Parse "a" extension and boxes from map fileEddie Hung2019-05-271-41/+60
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* | | Remove unused functionEddie Hung2019-05-271-23/+0
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* | | parse_xaiger to not parse symbol tableEddie Hung2019-05-271-64/+0
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* | | Instantiate cell type (from sym file) otherwise 'clean' warningsEddie Hung2019-05-271-3/+6
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* | | Add 'cinput' and 'coutput' to symbols file for boxesEddie Hung2019-05-271-0/+35
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* | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-231-5/+9
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| * | Rename labelEddie Hung2019-05-211-6/+5
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| * | Try againEddie Hung2019-05-211-4/+10
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| * | Fix warningEddie Hung2019-05-211-3/+2
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-2112-72/+473
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| * | Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
| | | | | | | | | | | | Hit parser limit with 3M gate design. This commit fix it.
| * | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
| |\ \ | | | | | | | | Support for attributes on parameters and localparams for Verilog frontend
| | * | Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-142-2/+18
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| * | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-068-35/+366
| |\ \ | | | | | | | | Add specify parser
| | * | Add "real" keyword to ilang formatClifford Wolf2019-05-062-1/+8
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
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| | * | | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-033-2/+14
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| | * | | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-234-4/+86
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-10 21:58:58 +0000
39;dir' to the directories which are used when searching include\n"); log(" files\n"); log("\n"); log("The command 'verilog_defaults' can be used to register default options for\n"); log("subsequent calls to 'read_verilog'.\n"); log("\n"); log("Note that the Verilog frontend does a pretty good job of processing valid\n"); log("verilog input, but has not very good error reporting. It generally is\n"); log("recommended to use a simulator (for example Icarus Verilog) for checking\n"); log("the syntax of the code, rather than to rely on read_verilog for that.\n"); log("\n"); } virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; bool flag_dump_vlog = false; bool flag_nolatches = false; bool flag_nomeminit = false; bool flag_nomem2reg = false; bool flag_mem2reg = false; bool flag_ppdump = false; bool flag_nopp = false; bool flag_nodpi = false; bool flag_lib = false; bool flag_noopt = false; bool flag_icells = false; bool flag_ignore_redef = false; bool flag_defer = false; std::map<std::string, std::string> defines_map; std::list<std::string> include_dirs; std::list<std::string> attributes; frontend_verilog_yydebug = false; sv_mode = false; formal_mode = false; default_nettype_wire = true; log_header(design, "Executing Verilog-2005 frontend.\n"); args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-sv") { sv_mode = true; continue; } if (arg == "-formal") { formal_mode = true; continue; } if (arg == "-dump_ast1") { flag_dump_ast1 = true; continue; } if (arg == "-dump_ast2") { flag_dump_ast2 = true; continue; } if (arg == "-dump_vlog") { flag_dump_vlog = true; continue; } if (arg == "-yydebug") { frontend_verilog_yydebug = true; continue; } if (arg == "-nolatches") { flag_nolatches = true; continue; } if (arg == "-nomeminit") { flag_nomeminit = true; continue; } if (arg == "-nomem2reg") { flag_nomem2reg = true; continue; } if (arg == "-mem2reg") { flag_mem2reg = true; continue; } if (arg == "-ppdump") { flag_ppdump = true; continue; } if (arg == "-nopp") { flag_nopp = true; continue; } if (arg == "-nodpi") { flag_nodpi = true; continue; } if (arg == "-lib") { flag_lib = true; defines_map["BLACKBOX"] = string(); continue; } if (arg == "-noopt") { flag_noopt = true; continue; } if (arg == "-icells") { flag_icells = true; continue; } if (arg == "-ignore_redef") { flag_ignore_redef = true; continue; } if (arg == "-defer") { flag_defer = true; continue; } if (arg == "-noautowire") { default_nettype_wire = false; continue; } if (arg == "-setattr" && argidx+1 < args.size()) { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; } if (arg == "-D" && argidx+1 < args.size()) { std::string name = args[++argidx], value; size_t equal = name.find('=', 2); if (equal != std::string::npos) { value = arg.substr(equal+1); name = arg.substr(0, equal); } defines_map[name] = value; continue; } if (arg.compare(0, 2, "-D") == 0) { size_t equal = arg.find('=', 2); std::string name = arg.substr(2, equal-2); std::string value; if (equal != std::string::npos) value = arg.substr(equal+1); defines_map[name] = value; continue; } if (arg == "-I" && argidx+1 < args.size()) { include_dirs.push_back(args[++argidx]); continue; } if (arg.compare(0, 2, "-I") == 0) { include_dirs.push_back(arg.substr(2)); continue; } break; } extra_args(f, filename, args, argidx); log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); AST::current_filename = filename; AST::set_line_num = &frontend_verilog_yyset_lineno; AST::get_line_num = &frontend_verilog_yyget_lineno; current_ast = new AST::AstNode(AST::AST_DESIGN); lexin = f; std::string code_after_preproc; if (!flag_nopp) { code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, include_dirs); if (flag_ppdump) log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str()); lexin = new std::istringstream(code_after_preproc); } frontend_verilog_yyset_lineno(1); frontend_verilog_yyrestart(NULL); frontend_verilog_yyparse(); frontend_verilog_yylex_destroy(); for (auto &child : current_ast->children) { if (child->type == AST::AST_MODULE) for (auto &attr : attributes) if (child->attributes.count(attr) == 0) child->attributes[attr] = AST::AstNode::mkconst_int(1, false); } if (flag_nodpi) error_on_dpi_function(current_ast); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; delete current_ast; current_ast = NULL; log("Successfully finished Verilog frontend.\n"); } } VerilogFrontend; struct VerilogDefaults : public Pass { VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" verilog_defaults -add [options]\n"); log("\n"); log("Add the specified options to the list of default options to read_verilog.\n"); log("\n"); log("\n"); log(" verilog_defaults -clear\n"); log("\n"); log("Clear the list of Verilog default options.\n"); log("\n"); log("\n"); log(" verilog_defaults -push\n"); log(" verilog_defaults -pop\n"); log("\n"); log("Push or pop the list of default options to a stack. Note that -push does\n"); log("not imply -clear.\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design*) { if (args.size() == 0) cmd_error(args, 1, "Missing argument."); if (args[1] == "-add") { verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end()); return; } if (args.size() != 2) cmd_error(args, 2, "Extra argument."); if (args[1] == "-clear") { verilog_defaults.clear(); return; } if (args[1] == "-push") { verilog_defaults_stack.push_back(verilog_defaults); return; } if (args[1] == "-pop") { if (verilog_defaults_stack.empty()) { verilog_defaults.clear(); } else { verilog_defaults.swap(verilog_defaults_stack.back()); verilog_defaults_stack.pop_back(); } return; } } } VerilogDefaults; YOSYS_NAMESPACE_END // the yyerror function used by bison to report parser errors void frontend_verilog_yyerror(char const *fmt, ...) { va_list ap; char buffer[1024]; char *p = buffer; p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ", YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); va_start(ap, fmt); p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); va_end(ap); p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); YOSYS_NAMESPACE_PREFIX log_error("%s", buffer); exit(1); }
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-10 21:58:58 +0000