aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Collapse)AuthorAgeFilesLines
* Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add specify parserClifford Wolf2019-04-234-33/+243
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #952 from YosysHQ/clifford/fix370Clifford Wolf2019-04-221-3/+18
|\ | | | | Determine correct signedness and expression width in for-loop unrolling
| * Determine correct signedness and expression width in for loop unrolling, ↵Clifford Wolf2019-04-221-3/+18
| | | | | | | | | | | | fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add log_debug() frameworkClifford Wolf2019-04-221-2/+0
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-221-1/+20
|\ | | | | support repeat loops with constant repeat counts outside of constant functions
| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-091-1/+20
| |
* | Add "noblackbox" attributeClifford Wolf2019-04-211-17/+27
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | New behavior for front-end handling of whiteboxesClifford Wolf2019-04-205-34/+100
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-185-11/+42
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "read_ilang -lib"Clifford Wolf2019-04-053-3/+14
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read -verific" and "read -noverific"Clifford Wolf2019-03-271-6/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-15/+71
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-213-15/+42
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-198-110/+348
|\
| * fix local name resolution in prefix constructsZachary Snow2019-03-181-1/+5
| |
| * Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve handling of memories used in mem index expressions on LHS of an ↵Clifford Wolf2019-03-121-5/+16
| | | | | | | | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-102-92/+66
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-095-56/+201
| |\ | | | | | | Add support for using SVA labels in yosys-smtbmc console output
| | * Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-082-44/+113
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add support for SVA labels in read_verilogClifford Wolf2019-03-073-26/+89
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add hack for handling SVA labels via VerificClifford Wolf2019-03-071-1/+14
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Update help message for -chparamEddie Hung2019-03-091-1/+2
| | |
| * | Add -chparam option to verific commandEddie Hung2019-03-091-2/+18
| | |
| * | Fix spellingEddie Hung2019-03-091-1/+1
| | |
| * | Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-15/+18
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
| |\ | | | | | | Fix error for wire decl in always block, fixes 763
| | * Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-022-0/+20
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve "read" error msgClifford Wolf2019-02-281-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Check if Verific was built with DB_PRESERVE_INITIAL_VALUEClifford Wolf2019-02-241-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fixes related to handling of autowires and upto-ranges, fixes #814Clifford Wolf2019-02-212-9/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix handling of expression width in $past, fixes #810Clifford Wolf2019-02-211-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix segfault in printing of some internal error messagesClifford Wolf2019-02-211-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add author nameEddie Hung2019-03-191-0/+1
| |
* | Fix for using POSIX basenameEddie Hung2019-02-191-2/+4
| |
* | Missing OSX headers?Eddie Hung2019-02-171-0/+5
| |
* | read_aiger to ignore line after ands for ascii, not binaryEddie Hung2019-02-171-2/+1
| |
* | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-171-5/+4
|\|
| * Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 05:10:49 +0000