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* verilog: fix $past's signednessJannis Harder2022-05-252-1/+2
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* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+1
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* fix text to fit 80 columnsMiodrag Milanovic2022-05-231-6/+9
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* Update verific command file documentationMiodrag Milanovic2022-05-231-17/+19
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* Use analysis mode if set in fileMiodrag Milanovic2022-05-231-2/+2
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* verific: Use new value change logic also for $stable of wide signals.Jannis Harder2022-05-111-7/+29
| | | | I missed this in the previous PR.
* Merge pull request #3305 from jix/sva_value_change_logicJannis Harder2022-05-091-10/+25
|\ | | | | verific: Improve logic generated for SVA value change expressions
| * verific: Improve logic generated for SVA value change expressionsJannis Harder2022-05-091-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation
* | verific: Fix conditions of SVAs with explicit clocks within proceduresJannis Harder2022-05-033-5/+16
|/ | | | | | | | | For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case.
* Ignore merging past ffs that we are not properly mergingMiodrag Milanovic2022-04-291-0/+1
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* verific: allow memories to be inferred in loops (vhdl)Miodrag Milanovic2022-04-181-0/+1
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* verific: allow memories to be inferred in loopsN. Engelhardt2022-04-151-0/+1
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* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-051-1/+11
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* Preserve internal wires for external netsMiodrag Milanovic2022-04-011-1/+1
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* Fix valgrind tests when using verificMiodrag Milanovic2022-03-301-0/+8
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* Properly mark modules importedMiodrag Milanovic2022-03-261-2/+2
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* Import verific netlist in consistent orderMiodrag Milanovic2022-03-252-23/+27
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* Merge pull request #3206 from YosysHQ/micko/quote_removeMiodrag Milanović2022-03-041-1/+4
|\ | | | | Remove quotes if any from attribute
| * Remove quotes if any from attributeMiodrag Milanovic2022-02-161-1/+4
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* | fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-181-3/+31
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* verilog: support for time scale delay valuesZachary Snow2022-02-142-4/+16
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-142-6/+18
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-17/+34
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-3/+11
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* Merge pull request #3164 from zachjs/fix-ast-warnMiodrag Milanović2022-02-111-1/+1
|\ | | | | fix dumpAst() compilation warning
| * fix dumpAst() compilation warningZachary Snow2022-01-181-1/+1
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* | Add ability to override verilog mode for verific -f commandMiodrag Milanovic2022-02-091-2/+44
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* | Use bmux for NTO1MUXMiodrag Milanovic2022-02-021-16/+2
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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+127
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-2/+9
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* sv: fix size cast clipping expression widthZachary Snow2022-01-031-1/+2
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* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-2/+5
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+10
| | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* Add YOSYS to the implicitly defined verilog macros in verificClaire Xenia Wolf2021-12-131-1/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Merge pull request #3102 from YosysHQ/claire/enumxzMiodrag Milanović2021-12-101-1/+1
|\ | | | | Fix verific import of enum values with x and/or z
| * Fix verific import of enum values with x and/or zClaire Xenia Wolf2021-12-101-1/+1
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Update verific.ccClaire Xen2021-12-101-4/+7
| | | | | | Ad-hoc fixes/improvements
* | If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
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* Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
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* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-7/+23
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* No need to alocate more memory than usedMiodrag Milanovic2021-11-101-1/+0
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* genrtlil: Fix displaying debug info in packagesKamil Rakoczy2021-11-101-1/+2
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Add "verific -cfg" commandClaire Xenia Wolf2021-11-011-2/+75
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix verific gclk handling for async-load FFsClaire Xenia Wolf2021-10-311-12/+67
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
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* Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-271-4/+1
| | | | This reverts commit b8624ad2aef941776f5b4a08f66f8d43e70f8467.
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-41/+291
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-24/+57
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-251-1/+4
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* Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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