| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | Use log_warning which does not immediately terminate. | litghost | 2018-08-03 | 1 | -3/+3 | |
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| * | | | | Add BLIF parsing support for .conn and .cname | litghost | 2018-08-02 | 1 | -3/+30 | |
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| * | | | | Verific: Produce errors for instantiating unknown module | Clifford Wolf | 2018-07-22 | 1 | -0/+3 | |
| | |_|/ |/| | | | | | | | | | | | | | | | | | | | | Because if the unknown module is connected to any constants, Verific will actually break all constants in the same module, even if they have nothing to do structurally with that instance of an unknown module. Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 4 | -137/+131 | |
| | | | | | | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | |||||
| * | | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 3 | -82/+79 | |
| | | | | | | | | | | | | | Wherever we can report a source-level location. | |||||
| * | | | Provide source-location logging. | Henner Zeller | 2018-07-19 | 1 | -3/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil. | |||||
| * | | | Fix handling of eventually properties in verific importer | Clifford Wolf | 2018-07-17 | 1 | -2/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Fix verific -vlog-incdir and -vlog-libdir handling | Clifford Wolf | 2018-07-16 | 1 | -2/+13 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Fix "read -incdir" | Clifford Wolf | 2018-07-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "read -incdir" | Clifford Wolf | 2018-07-16 | 1 | -0/+19 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Fix verific eventually handling | Clifford Wolf | 2018-06-29 | 1 | -6/+5 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add verific support for eventually properties | Clifford Wolf | 2018-06-29 | 1 | -5/+105 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "verific -formal" and "read -formal" | Clifford Wolf | 2018-06-29 | 1 | -7/+15 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "read -sv -D" support | Clifford Wolf | 2018-06-28 | 1 | -2/+25 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "read -undef" | Clifford Wolf | 2018-06-28 | 1 | -0/+32 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Fix handling of signed memories | Clifford Wolf | 2018-06-28 | 1 | -0/+3 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add YOSYS_NOVERIFIC env variable for temporarily disabling verific | Clifford Wolf | 2018-06-22 | 1 | -22/+40 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add simplified "read" command, enable extnets in implicit Verific import | Clifford Wolf | 2018-06-21 | 1 | -0/+84 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add automatic verific import in hierarchy command | Clifford Wolf | 2018-06-20 | 2 | -0/+56 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Bugfix in liberty parser (as suggested by aiju in #569) | Clifford Wolf | 2018-06-15 | 1 | -1/+1 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 3 | -0/+20 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add comment to VIPER #13453 work-around | Clifford Wolf | 2018-05-28 | 1 | -0/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix Verific handling of single-bit anyseq/anyconst wires | Clifford Wolf | 2018-05-25 | 1 | -2/+4 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE | Clifford Wolf | 2018-05-24 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix verific handling of anyconst/anyseq attributes | Clifford Wolf | 2018-05-24 | 2 | -16/+28 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Support SystemVerilog `` extension for macros | Jim Paris | 2018-05-17 | 1 | -1/+5 | |
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| * | | Skip spaces around macro arguments | Jim Paris | 2018-05-17 | 1 | -0/+1 | |
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| * | | Fix handling of anyconst/anyseq attrs in VHDL code via Verific | Clifford Wolf | 2018-05-15 | 1 | -6/+6 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Also interpret '&' in liberty functions | Sergiusz Bazanski | 2018-05-12 | 1 | -1/+1 | |
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| * | | Further improve handling of zero-length SVA consecutive repetition | Clifford Wolf | 2018-05-05 | 1 | -69/+108 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix handling of zero-length SVA consecutive repetition | Clifford Wolf | 2018-05-05 | 1 | -26/+46 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 4 | -19/+56 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Support more character literals | Dan Gisselquist | 2018-05-03 | 1 | -1/+9 | |
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| * | | Add statement labels for immediate assertions | Clifford Wolf | 2018-04-13 | 1 | -18/+21 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Allow "property" in immediate assertions | Clifford Wolf | 2018-04-12 | 1 | -17/+20 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add PRIM_HDL_ASSERTION support to Verific importer | Clifford Wolf | 2018-04-07 | 1 | -3/+19 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix handling of $global_clocking in Verific | Clifford Wolf | 2018-04-06 | 1 | -1/+7 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add read_verilog anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -1/+33 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add Verific anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -2/+36 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add "verific -autocover" | Clifford Wolf | 2018-04-06 | 2 | -5/+17 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Set RAM runtime flags for Verific frontend | makaimann | 2018-04-05 | 1 | -0/+3 | |
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| * | | Remove left-over log_ping debug commands.. oops. | Clifford Wolf | 2018-03-31 | 1 | -4/+0 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 2 | -2/+170 | |
| | | | | | | | | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | |||||
| * | | Fix handling of unclocked immediate assertions in Verific front-end | Clifford Wolf | 2018-03-26 | 3 | -17/+42 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Update todo for more features to verificsva.cc | Clifford Wolf | 2018-03-16 | 1 | -3/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Update todo for more features to verificsva.cc | Clifford Wolf | 2018-03-16 | 1 | -0/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add todo for more features to verificsva.cc | Clifford Wolf | 2018-03-16 | 1 | -8/+45 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Improve import of memories via Verific | Clifford Wolf | 2018-03-15 | 1 | -16/+23 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix handling of SV compilation units in Verific front-end | Clifford Wolf | 2018-03-14 | 1 | -28/+25 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEAT | Clifford Wolf | 2018-03-10 | 1 | -15/+72 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
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index : iCE40/yosys | |
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