iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	2	-6/+10
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	2	-1/+9
*	Allow defining input ports as "input logic" in SystemVerilog	Ruben Undheim	2016-06-20	1	-2/+2
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	2	-0/+33
*	Small improvements in Verilog front-end docs	Clifford Wolf	2016-05-20	1	-0/+3
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	1	-2/+6
*	Fixed Verilog parser fix and more similar improvements	Clifford Wolf	2016-03-15	1	-18/+9
*	Use left-recursive rule for cell_port_list in Verilog parser.	Andrew Becker	2016-03-15	1	-6/+10
*	Fixed typos in verilog_defaults help message	Clifford Wolf	2016-03-10	1	-3/+3
*	Fixed handling of parameters and localparams in functions	Clifford Wolf	2015-11-11	1	-1/+1
*	Fixed bug in verilog parser	Clifford Wolf	2015-10-15	1	-1/+1
*	SystemVerilog also has assume(), added implicit -D FORMAL	Clifford Wolf	2015-10-13	3	-4/+5
*	Added support for "parameter" and "localparam" in global context	Clifford Wolf	2015-10-07	1	-0/+2
*	Added read_verilog -nodpi	Clifford Wolf	2015-09-23	1	-0/+19
*	Fixed support for $write system task	Clifford Wolf	2015-09-23	1	-1/+1
*	Fixed detection of "task foo(bar);" syntax error	Clifford Wolf	2015-09-22	1	-0/+2
*	Fixed segfault on invalid verilog constant 1'b_	Clifford Wolf	2015-09-22	1	-1/+1
*	Small corrections to const2ast warning messages	Clifford Wolf	2015-08-17	1	-2/+2
*	Check base-n literals only contain valid digits	Florian Zeitz	2015-08-17	1	-0/+3
*	Warn on literals exceeding the specified bit width	Florian Zeitz	2015-08-17	1	-34/+39
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	2	-3/+3
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-6/+6
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12	3	-4/+6
*	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11	1	-2/+7
*	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01	1	-1/+8
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	6	-16/+16
*	Verilog front-end: define `BLACKBOX in -lib mode	Clifford Wolf	2015-04-19	1	-1/+2
*	Ignore celldefine directive in verilog front-end	Clifford Wolf	2015-03-25	1	-0/+3
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	4	-5/+25
*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20	1	-7/+20
*	YosysJS stuff	Clifford Wolf	2015-02-19	1	-0/+1
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	1	-1/+15
*	Fixed handling of "//" in filenames in verilog pre-processor	Clifford Wolf	2015-02-14	2	-1/+5
*	Improved read_verilog support for empty behavioral statements	Clifford Wolf	2015-02-10	1	-6/+2
*	Ignoring more system task and functions	Clifford Wolf	2015-01-15	1	-1/+1
*	Enable bison to be customized	Fabio Utzig	2015-01-08	1	-1/+1
*	Define YOSYS and SYNTHESIS in preproc	Clifford Wolf	2015-01-02	1	-1/+2
*	Improved some warning messages	Clifford Wolf	2014-12-27	1	-6/+18
*	Fixed supply0/supply1 with many wires	Clifford Wolf	2014-12-11	1	-3/+15
*	Fixed minor bug in parsing delays	Clifford Wolf	2014-11-24	1	-1/+4
*	Fixed two minor bugs in constant parsing	Clifford Wolf	2014-11-24	2	-3/+7
*	Added warning for use of 'z' constants in HDL	Clifford Wolf	2014-11-14	3	-6/+14
*	Fixed parsing of nested verilog concatenation and replicate	Clifford Wolf	2014-11-12	1	-1/+1
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-6/+6
*	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	Clifford Wolf	2014-10-30	1	-4/+5
*	Added support for task and function args in parentheses	Clifford Wolf	2014-10-27	1	-6/+45
*	Re-introduced Yosys::readsome() helper function	Clifford Wolf	2014-10-23	2	-10/+4
*	Print "SystemVerilog" in "read_verilog -sv" log messages	Clifford Wolf	2014-10-16	1	-1/+1