| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 1 | -1/+7 |
| * | | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -2/+6 |
| * | | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 1 | -0/+11 |
| * | | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 |
| * | | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 1 | -2/+12 |
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| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 1 | -1/+10 |
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| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 1 | -1/+10 |
| * | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 1 | -1/+1 |
| * | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int... | Clifford Wolf | 2019-06-07 | 1 | -1/+10 |
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| | * | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 1 | -9/+17 |
| * | | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 |
| * | | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 |
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| * | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 1 | -2/+2 |
| * | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 1 | -1/+7 |
| * | | Merge pull request #1013 from antmicro/parameter_attributes | Clifford Wolf | 2019-05-16 | 1 | -2/+2 |
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| | * | | Added support for parsing attributes on parameters in Verilog frontent. Conte... | Maciej Kurc | 2019-05-16 | 1 | -2/+2 |
| * | | | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 1 | -1/+9 |
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| * | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -22/+295 |
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| | * \ | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -2/+8 |
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| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -8/+18 |
| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -20/+18 |
| | * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -2/+67 |
| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | * | | | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -22/+222 |
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| * | | | verilog_parser: Fix Bison warning | Ben Widawsky | 2019-05-05 | 1 | -1/+1 |
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| * | | Merge pull request #988 from YosysHQ/clifford/fix987 | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
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| | * | | Add approximate support for SV "var" keyword, fixes #987 | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
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| * / | Add support for SVA "final" keyword | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
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| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -5/+5 |
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -5/+5 |
| * | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 1 | -43/+56 |
| * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 1 | -39/+61 |
| * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 1 | -23/+79 |
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -3/+3 |
| * | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 |
| * | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 |
| * | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 |
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars... | Udi Finkelstein | 2018-10-25 | 1 | -14/+14 |
| * | Handle FIXME for modport members without type directly in front | Ruben Undheim | 2018-10-13 | 1 | -6/+8 |
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -3/+21 |
| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+60 |
| * | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 1 | -5/+18 |
| * | Added support for ommited "parameter" in Verilog-2001 style parameter decl in... | Clifford Wolf | 2018-09-23 | 1 | -3/+9 |
| * | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 |
| * | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout... | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 |
| * | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 |
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+6 |
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| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -0/+1 |
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+5 |
| * | | Detect illegal port declaration, e.g input/output/inout keyword must be the f... | Udi Finkelstein | 2018-06-06 | 1 | -3/+6 |
