| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | frontend: cleanup to use more ID::*, more dict<> instead of map<> | Eddie Hung | 2020-05-04 | 1 | -1/+1 |
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| * | Merge pull request #1811 from PeterCrozier/typedef_scope | N. Engelhardt | 2020-03-30 | 1 | -2/+3 |
| |\ | | | | | Support module/package/interface/block scope for typedef names. | ||||
| | * | Support module/package/interface/block scope for typedef names. | Peter Crozier | 2020-03-23 | 1 | -2/+3 |
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| * | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 1 | -4/+0 |
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly. | ||||
| * | Parser changes to support typedef. | Peter | 2020-03-22 | 1 | -0/+6 |
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| * | Closes #1717. Add more precise Verilog source location information to AST ↵ | Alberto Gonzalez | 2020-02-23 | 1 | -1/+0 |
| | | | | | and RTLIL nodes. | ||||
| * | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -5/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -2/+5 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -0/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 1 | -0/+9 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -1/+2 |
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| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 1 | -0/+6 |
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| * | No tristate warning message for "read_verilog -lib" | Clifford Wolf | 2016-07-23 | 1 | -0/+3 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -0/+3 |
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| * | Added warning for use of 'z' constants in HDL | Clifford Wolf | 2014-11-14 | 1 | -1/+1 |
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| * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 1 | -1/+4 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -1/+5 |
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| * | Added read_verilog -sv options, added support for bit, logic, | Clifford Wolf | 2014-06-12 | 1 | -0/+3 |
| | | | | | allways_ff, always_comb, and always_latch | ||||
| * | Added Verilog support for "`default_nettype none" | Clifford Wolf | 2014-02-17 | 1 | -0/+3 |
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| * | Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵ | Clifford Wolf | 2013-11-22 | 1 | -3/+0 |
| | | | | | flex) | ||||
| * | Added support for include directories with the new '-I' argument of the | Johann Glaser | 2013-08-20 | 1 | -1/+2 |
| | | | | | 'read_verilog' command | ||||
| * | added option '-Dname[=definition]' to command 'read_verilog' | Johann Glaser | 2013-05-19 | 1 | -1/+1 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+62 |
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index : iCE40/yosys | |
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