iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Added verilog_defaults command	Clifford Wolf	2014-01-17	1	-0/+66
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	1	-1/+10
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22	1	-2/+0
*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20	1	-1/+10
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	1	-12/+11
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-1/+10
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19	1	-1/+16
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-1/+9
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-1/+11
*	Added help messages to ilang and verilog frontends	Clifford Wolf	2013-03-01	1	-1/+46
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+148