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* Fix argument handling in connect_rpcClaire Xenia Wolf2020-10-191-1/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-1/+1
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Use C++11 final/override keywords.whitequark2020-06-181-8/+8
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* Add WASI platform support.whitequark2020-04-301-1/+1
| | | | | | | | | | | | This includes the following significant changes: * Patching ezsat and minisat to disable resource limiting code on WASM/WASI, since the POSIX functions they use are unavailable. * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform does not support spawning subprocesses (i.e. Emscripten or WASI). This definition hides the definition of `run_command()`. * Adding a new Makefile flag, DISABLE_SPAWN, present in the same condition. This flag disables all passes that require spawning subprocesses for their function.
* ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-181-0/+2
| | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* kernel: use more ID::*Eddie Hung2020-04-021-1/+1
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* kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-1/+1
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* Fix compilation for emccjiegec2020-03-111-1/+2
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* Fixes for MSVC buildMiodrag Milanovic2019-10-041-2/+6
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* Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
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* rpc: new frontend.whitequark2019-09-302-0/+591
A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.