iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24	2	-1/+8
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	2	-5/+1
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	2	-1/+8
*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20	1	-1/+1
*	Fixed parsing of value-less attributes in ilang	Clifford Wolf	2013-10-23	1	-1/+1
*	Fixed memory leak in ilang frontend	Clifford Wolf	2013-05-23	1	-0/+1
*	Added help messages to ilang and verilog frontends	Clifford Wolf	2013-03-01	1	-1/+11
*	added .gitignore files	Clifford Wolf	2013-01-05	1	-0/+4
*	initial import	Clifford Wolf	2013-01-05	5	-0/+648