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* Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
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* Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-1/+8
|\ | | | | Add specify parser
| * Add "real" keyword to ilang formatClifford Wolf2019-05-062-1/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_ilang -lib"Clifford Wolf2019-04-053-3/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
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* Add "make coverage"Clifford Wolf2018-08-273-6/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-1/+7
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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-142-1/+8
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Fixed oom bug in ilang parserClifford Wolf2015-11-291-2/+2
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* Fixed performance bug in ilang parserClifford Wolf2015-11-271-6/+12
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
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* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-123-4/+6
| | | | This is based on work done by Larry Doolittle
* Fixed trailing whitespacesClifford Wolf2015-07-024-8/+8
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* Enable bison to be customizedFabio Utzig2015-01-081-1/+1
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* Fixed memory->start_offset handlingClifford Wolf2015-01-011-0/+3
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
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* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-231-5/+1
| | | | (f.read() + f.gcount() made problems with lines > 16kB)
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-151-4/+4
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* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-153-13/+17
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* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-111-1/+1
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* namespace YosysClifford Wolf2014-09-272-3/+5
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-234-6/+10
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* Added module->portsClifford Wolf2014-08-141-0/+1
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-2/+2
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-2/+2
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-313-4/+15
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* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-282-1/+5
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* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-271-10/+10
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-3/+2
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-1/+1
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-3/+3
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-4/+1
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* Added "make PRETTY=1"Clifford Wolf2014-07-241-3/+3
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-2/+2
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-2/+2
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* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-221-37/+6
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-14/+14
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-14/+14
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* Fixed ilang parsing of process attributesClifford Wolf2014-07-221-0/+1
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* Fixed make rules for ilang parserClifford Wolf2014-07-221-1/+3
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* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-212-25/+10
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* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-201-0/+7
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* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-201-1/+1
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* Bugfix in ilang frontend autoidx recoveryClifford Wolf2014-03-071-2/+2
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