| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -4/+9 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places. | ||||
| * | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 1 | -1/+9 |
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| * | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -1/+8 |
| |\ | | | | | Add specify parser | ||||
| | * | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 2 | -1/+8 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix the other bison warning in ilang_parser.y | Clifford Wolf | 2019-05-06 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 3 | -3/+14 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "read_ilang -[no]overwrite" | Clifford Wolf | 2018-12-23 | 3 | -4/+54 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | read_ilang: allow slicing sigspecs. | whitequark | 2018-12-16 | 1 | -10/+6 |
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| * | Add "make coverage" | Clifford Wolf | 2018-08-27 | 3 | -6/+5 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -1/+7 |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 2 | -1/+8 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Fixed oom bug in ilang parser | Clifford Wolf | 2015-11-29 | 1 | -2/+2 |
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| * | Fixed performance bug in ilang parser | Clifford Wolf | 2015-11-27 | 1 | -6/+12 |
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| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
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| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 3 | -4/+6 |
| | | | | | This is based on work done by Larry Doolittle | ||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 4 | -8/+8 |
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| * | Enable bison to be customized | Fabio Utzig | 2015-01-08 | 1 | -1/+1 |
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| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 1 | -0/+3 |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
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| * | Re-introduced Yosys::readsome() helper function | Clifford Wolf | 2014-10-23 | 1 | -5/+1 |
| | | | | | (f.read() + f.gcount() made problems with lines > 16kB) | ||||
| * | Updated .gitignore file for ilang and verilog frontends | Clifford Wolf | 2014-10-15 | 1 | -4/+4 |
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| * | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 3 | -13/+17 |
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| * | Fixed win32 troubles with f.readsome() | Clifford Wolf | 2014-10-11 | 1 | -1/+1 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 2 | -3/+5 |
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| * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 4 | -6/+10 |
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| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -0/+1 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
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| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 3 | -4/+15 |
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| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 2 | -1/+5 |
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| * | Fixed ilang parser for new RTLIL API | Clifford Wolf | 2014-07-27 | 1 | -10/+10 |
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| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -3/+2 |
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| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -3/+3 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -4/+1 |
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| * | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 | 1 | -3/+3 |
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| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
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| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
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| * | SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only | Clifford Wolf | 2014-07-22 | 1 | -37/+6 |
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| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -14/+14 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -14/+14 |
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| * | Fixed ilang parsing of process attributes | Clifford Wolf | 2014-07-22 | 1 | -0/+1 |
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| * | Fixed make rules for ilang parser | Clifford Wolf | 2014-07-22 | 1 | -1/+3 |
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| * | Added "autoidx" statement to ilang file format | Clifford Wolf | 2014-07-21 | 2 | -25/+10 |
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| * | Fixed clang -Wdeprecated-register warnings | Clifford Wolf | 2014-04-20 | 1 | -0/+7 |
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| * | Replaced depricated %name-prefix= bison directive | Clifford Wolf | 2014-04-20 | 1 | -1/+1 |
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