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* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-182-4/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-212-10/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* fix local name resolution in prefix constructsZachary Snow2019-03-181-1/+5
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* Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve handling of memories used in mem index expressions on LHS of an ↵Clifford Wolf2019-03-121-5/+16
| | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-092-3/+10
|\ | | | | Add support for using SVA labels in yosys-smtbmc console output
| * Add support for SVA labels in read_verilogClifford Wolf2019-03-072-3/+10
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-15/+18
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
|\ | | | | Fix error for wire decl in always block, fixes 763
| * Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-022-0/+20
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes related to handling of autowires and upto-ranges, fixes #814Clifford Wolf2019-02-212-9/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of expression width in $past, fixes #810Clifford Wolf2019-02-211-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault in printing of some internal error messagesClifford Wolf2019-02-211-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-2/+2
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵Clifford Wolf2018-11-011-2/+15
| | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
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* Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-3/+105
| | | | test case
* Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-184-14/+265
|\ | | | | Support for SystemVerilog interfaces and modports
| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
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| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-123-5/+68
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-124-14/+175
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ | |/ |/| Fix issue #630
| * Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| | | | | | | | (as well as a non critical minor code optimization)
| * Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-184-237/+254
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| * | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
* | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
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* | | Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-232-8/+11
| | | | | | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
* | Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-4/+4
|\ \ | | | | | | Consistent use of 'override' for virtual methods in derived classes.
| * | Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* | | Merge pull request #590 from hzeller/remaining-file-errorClifford Wolf2018-08-151-15/+15
|\ \ \ | | | | | | | | Fix remaining log_file_error(); emit dependent file references in new…
| * | | Fix remaining log_file_error(); emit dependent file references in new line.Henner Zeller2018-07-201-15/+15
| |/ / | | | | | | | | | | | | | | | | | | There are some places that reference dependent file locations ("this function was called from ..."). These are now in a separate line for ease of jumping to it with the editor (behaves similarly to compilers that emit dependent messages).
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