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* Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-291-2/+2
|\ | | | | ast/simplify: don't bitblast async ROMs declared as `logic`
| * ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-051-2/+2
| | | | | | | | Fixes #2020.
* | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-1/+20
| | | | | | | | Fixes #2058.
* | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-1/+1
|\ \ | | | | | | ast: swap range regardless of range_left >= 0
| * | ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
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* | | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-082-4/+5
|\ \ \ | | | | | | | | Avoid switch fall-through warnings
| * | | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-072-4/+5
| | | | | | | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* | | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-074-14/+80
|\ \ \ \ | |/ / / |/| | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-024-5/+20
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-024-7/+53
| | |/ | |/| | | | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-052-13/+13
|\ \ \ | | | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>
| * | | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-042-13/+13
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* / | verilog: set src attribute for primitivesEddie Hung2020-05-041-1/+3
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* | Merge pull request #1996 from boqwxp/rtlil_source_locationsEddie Hung2020-05-041-13/+13
|\ \ | |/ |/| frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
| * frontend: Include complete source location instead of just ↵Alberto Gonzalez2020-05-011-13/+13
| | | | | | | | `location.first_line` in `frontends/ast/genrtlil.cc`.
* | Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
|/ | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-212-3/+4
| | | | Fixes #1819, #1820.
* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-214-15/+207
|\ | | | | Improved rewrite code for writing to bit slice
| * Make mask-and-shift the default for bitselwriteClaire Wolf2020-04-161-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-164-4/+144
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * Improved rewrite code for writing to bit slice (disabled for now)Claire Wolf2020-04-151-12/+64
| | | | | | | | | | | | | | | | | | This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #1961 from whitequark/paramod-original-namewhitequark2020-04-211-0/+3
|\ \ | | | | | | ast, rpc: record original name of $paramod\* as \hdlname attribute
| * | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* | | Extend support for format strings in Verilog front-endClaire Wolf2020-04-181-8/+38
|/ / | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* / ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-162-2/+7
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1918 from whitequark/simplify-improve_enumwhitequark2020-04-151-5/+3
|\ | | | | ast/simplify: improve enum handling
| * ast/simplify: improve enum handling.whitequark2020-04-151-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, enum values were serialized as attributes of form \enum_<width>_<value> where <value> was a decimal signed integer. This has multiple drawbacks: * Enums with large values would be hard to process for downstream tooling that cannot parse arbitrary precision decimals. (In fact Yosys also did not correctly process enums with large values, and would overflow `int`.) * Enum value attributes were not confined to their own namespace, making it harder for downstream tooling to enumerate all such attributes, as opposed to looking up any specific value. * Enum values could not include x or z, which are explicitly permitted in the SystemVerilog standard. After this commit, enum values are serialized as attributes of form \enum_value_<value> where <value> is a bit sequence of the appropriate width.
* | Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-0/+23
|\ \ | | | | | | support using previously declared types/localparams/parameters in package
| * | support using previously declared types/localparams/params in packageJeff Wang2020-04-071-0/+23
| |/ | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* / duplicated enum item names should result in an errorJeff Wang2020-04-071-2/+3
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* Merge pull request #1853 from YosysHQ/eddie/fix_dynsliceEddie Hung2020-04-021-1/+2
|\ | | | | ast: cap dynamic range select to size of signal, suppresses warnings
| * ast: cap dynamic range select to size of signal, suppresses warningsEddie Hung2020-04-011-1/+2
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* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-023-182/+170
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* | kernel: use more ID::*Eddie Hung2020-04-023-53/+53
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* | Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-022-37/+43
|\ \ | | | | | | kernel: speedup by using more pass-by-const-ref
| * | kernel: more pass by const ref, more speedupsEddie Hung2020-03-182-37/+43
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* | | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-1/+1
|\ \ \ | | |/ | |/| ast: simplify to fully populate dynamic slicing case transformation
| * | ast: simplify to fully populate dynamic slicing case transformationEddie Hung2020-03-311-1/+1
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* | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
|\ \ | | | | | | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
| * | Add explanatory comment about inefficient wire removal and remove ↵Alberto Gonzalez2020-03-301-4/+8
| | | | | | | | | | | | | | | | | | superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
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| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
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* | Merge pull request #1607 from whitequark/simplify-simplify-meminitClaire Wolf2020-03-271-63/+82
|\ \ | | | | | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
| * | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
* | | Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
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* | | Fix NDEBUG warningsEddie Hung2020-03-191-1/+1
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* | | Add precise locations for assertshuaixv2020-03-191-0/+1
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* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-034-267/+253
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
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