iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	1	-3/+3
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*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	1	-0/+1
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*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-1/+5
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+1
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-3/+3
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*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-1/+1
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-0/+1
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-3/+3
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	1	-1/+1
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-4/+4
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*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24	1	-1/+1
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*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-0/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+228