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* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-0/+2
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* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-0/+6
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* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-231-1/+7
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-211-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-121-0/+3
|/ | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* verilog: refactored constant function evaluationZachary Snow2021-02-041-4/+3
| | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* verilog: significant block scoping improvementsZachary Snow2021-01-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* verilog: improved support for recursive functionsZachary Snow2020-12-311-0/+2
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* Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-151-0/+1
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* Fix generate scoping issuesZachary Snow2020-07-311-1/+1
| | | | | | | | | - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+1
| | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* Use C++11 final/override keywords.whitequark2020-06-181-5/+5
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* Add latch detection for use_case_method in part-select write, fixes #2040Claire Wolf2020-06-041-0/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
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* Implement SV structs.Peter Crozier2020-05-081-2/+5
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* Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-0/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+2
| | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-0/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-4/+4
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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-1/+8
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-1/+8
| | | | | | | | and RTLIL nodes.
* | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-271-1/+1
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* Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-0/+7
|\ | | | | Enum support
| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | ast: Add support for $sformatf system functionDavid Shah2020-01-191-0/+1
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-2/+5
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-2/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-301-1/+1
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* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-201-0/+1
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-071-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-1/+3
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-1/+3
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+3
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+3
| |/ | | | | | | Includes work from @sumit0190 and @AaronKel
* | remove leftovers from ast data structuresStefan Biereigel2019-05-271-1/+0
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* | fix indentation across filesStefan Biereigel2019-05-231-1/+1
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* | implementation for assignments workingStefan Biereigel2019-05-231-0/+1
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* | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-1/+1
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* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-211-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-011-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-0/+5
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* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+3
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+6
| | | | This time doing the changes mostly in AST before RTLIL generation
* Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-231-2/+2
| | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
* Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-4/+4
|\ | | | | Consistent use of 'override' for virtual methods in derived classes.
| * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
| | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
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