iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+0
*	Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()	Clifford Wolf	2016-08-21	1	-4/+15
*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	1	-5/+16
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-0/+1
*	A few modifications after pull request comments	Ruben Undheim	2016-06-18	1	-2/+2
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	1	-0/+12
*	Include <cmath> in yosys.h	Clifford Wolf	2016-05-08	1	-9/+0
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	1	-1/+10
*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	1	-1/+1
*	Fixed segfault in AstNode::asReal	Clifford Wolf	2015-09-25	1	-1/+1
*	Fixed AstNode::mkconst_bits() segfault on zero-sized constant	Clifford Wolf	2015-09-24	1	-1/+1
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-4/+4
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	1	-0/+1
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	1	-2/+6
*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14	1	-1/+2
*	Added global yosys_celltypes	Clifford Wolf	2014-12-29	1	-1/+1
*	dict/pool changes in ast	Clifford Wolf	2014-12-29	1	-0/+4
*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28	1	-1/+1
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-1/+1
*	Fixed constant "cond ? string1 : string2" with strings of different size	Clifford Wolf	2014-10-25	1	-0/+2
*	minor indenting corrections	Clifford Wolf	2014-10-19	1	-2/+2
*	Builds on Mac 10.9.2 with LLVM 3.5.	Parviz Palangpour	2014-10-19	1	-0/+5
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11	1	-2/+2
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-0/+4
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21	1	-1/+22
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	1	-0/+1
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21	1	-12/+26
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18	1	-0/+8
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17	1	-1/+1
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15	1	-1/+1
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14	1	-2/+1
*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+1
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	1	-0/+7
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-2/+2
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	1	-27/+2
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-5/+5
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+5
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	1	-1/+4
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+2
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-0/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-5/+5
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16	1	-0/+2
*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15	1	-1/+1
*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15	1	-9/+12
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14	1	-0/+18
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	1	-4/+9
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14	1	-1/+30