| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | Bugfix in SMV back-end for partially unassigned wires | Clifford Wolf | 2015-08-05 | 1 | -4/+16 | |
| | | | ||||||
| * | | Added $assert support to SMV back-end | Clifford Wolf | 2015-08-04 | 1 | -4/+21 | |
| | | | ||||||
| * | | Improvements in BLIF back-end | Clifford Wolf | 2015-07-29 | 1 | -5/+84 | |
| | | | ||||||
| * | | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 13 | -114/+114 | |
| | | | ||||||
| * | | Added init support to SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -1/+3 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -64/+115 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -13/+59 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-18 | 1 | -24/+94 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-17 | 1 | -11/+72 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-17 | 1 | -11/+64 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-16 | 1 | -3/+46 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-15 | 1 | -2/+95 | |
| | | | ||||||
| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-15 | 1 | -7/+85 | |
| | | | ||||||
| * | | Added "write_smv" skeleton | Clifford Wolf | 2015-06-15 | 2 | -0/+261 | |
| | | | ||||||
| * | | Removed debug code from write_smt2 | Clifford Wolf | 2015-06-14 | 1 | -2/+0 | |
| | | | ||||||
| * | | Added write_smt2 -mem | Clifford Wolf | 2015-06-14 | 1 | -80/+157 | |
| | | | ||||||
| * | | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 | 2 | -2/+2 | |
| | | | ||||||
| * | | Improvements in cellaigs.cc and "json -aig" | Clifford Wolf | 2015-06-11 | 1 | -6/+63 | |
| | | | ||||||
| * | | AigMaker refactoring | Clifford Wolf | 2015-06-10 | 1 | -1/+1 | |
| | | | ||||||
| * | | Added "json -aig" | Clifford Wolf | 2015-06-10 | 1 | -9/+63 | |
| | | | ||||||
| * | | $mem cell in verilog backend : grouped writes by clock | luke whittlesey | 2015-06-08 | 1 | -54/+108 | |
| | | | ||||||
| * | | Bug fix in $mem verilog backend + changed tests/bram flow of make test. | luke whittlesey | 2015-06-04 | 1 | -14/+16 | |
| | | | ||||||
| * | | Improvements in BLIF front-end | Clifford Wolf | 2015-05-24 | 1 | -0/+1 | |
| | | | ||||||
| * | | Some fixes for $mem in verilog back-end | Clifford Wolf | 2015-05-20 | 1 | -19/+23 | |
| | | | ||||||
| * | | Merge pull request #63 from wluker/verilog-backend-mem | Clifford Wolf | 2015-05-11 | 1 | -1/+2 | |
| |\ \ | | | | | | | Fixed bug in $mem cell verilog code generation. | |||||
| | * | | Fixed bug in $mem cell verilog code generation. | luke whittlesey | 2015-05-11 | 1 | -11/+12 | |
| | | | | ||||||
| * | | | Disabled broken $mem support in verilog backend | Clifford Wolf | 2015-05-10 | 1 | -11/+11 | |
| |/ / | ||||||
| * | | Made changes recommended by Clifford Wolf ... | luke whittlesey | 2015-05-10 | 1 | -22/+11 | |
| | | | | | | | | | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector. | |||||
| * | | Verilog backend for $mem cells should now be able to handle different | luke whittlesey | 2015-05-08 | 1 | -50/+105 | |
| | | | | | | | | | write-enable bits and RD_TRANSPARENT parameter settings. | |||||
| * | | Added support for $mem cells in the verilog backend. | luke whittlesey | 2015-05-07 | 1 | -1/+120 | |
| | | | ||||||
| * | | Minor fixes in handling of "init" attribute | Clifford Wolf | 2015-04-09 | 1 | -7/+7 | |
| | | | ||||||
| * | | Removed "techmap -share_map" (use "-map +/filename" instead) | Clifford Wolf | 2015-04-08 | 1 | -1/+1 | |
| | | | ||||||
| * | | Added "port_directions" to write_json output | Clifford Wolf | 2015-04-06 | 1 | -0/+20 | |
| | | | ||||||
| * | | Added "init" attribute support to verilog backend | Clifford Wolf | 2015-04-04 | 1 | -0/+5 | |
| | | | ||||||
| * | | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 | |
| | | | | | | | corrected url | |||||
| * | | Delete btor.ys | Ahmed Irfan | 2015-04-03 | 1 | -18/+0 | |
| | | | | | | | .ys script not needed | |||||
| * | | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 | |
| | | | | | | | pmux cell is implemented | |||||
| * | | separated memory next from write cell | Ahmed Irfan | 2015-04-03 | 1 | -7/+55 | |
| | | | ||||||
| * | | Added Verilog backend $dffsr support | Clifford Wolf | 2015-03-18 | 1 | -1/+51 | |
| | | | ||||||
| * | | Documentation for JSON format, added attributes | Clifford Wolf | 2015-03-06 | 1 | -16/+156 | |
| | | | ||||||
| * | | Json bugfix | Clifford Wolf | 2015-03-03 | 1 | -1/+1 | |
| | | | ||||||
| * | | Json backend improvements | Clifford Wolf | 2015-03-03 | 1 | -4/+12 | |
| | | | ||||||
| * | | Added write_blif -attr | Clifford Wolf | 2015-03-02 | 1 | -18/+33 | |
| | | | ||||||
| * | | Added JSON backend | Clifford Wolf | 2015-03-02 | 2 | -0/+262 | |
| | | | ||||||
| * | | Added $assume support to write_smt2 | Clifford Wolf | 2015-02-26 | 1 | -4/+19 | |
| | | | ||||||
| * | | Minor "write_smt2" help msg change | Clifford Wolf | 2015-02-22 | 1 | -1/+1 | |
| | | | ||||||
| * | | Added "<mod>_a" and "<mod>_i" to write_smt2 output | Clifford Wolf | 2015-02-22 | 1 | -23/+149 | |
| | | | ||||||
| * | | Fixed "write_verilog -attr2comment" handling of "*/" in strings | Clifford Wolf | 2015-02-13 | 1 | -2/+4 | |
| |/ | ||||||
| * | Added EDIF backend support for multi-bit cell ports | Clifford Wolf | 2015-02-01 | 1 | -11/+10 | |
| | | ||||||
| * | Shorter "dump" options | Clifford Wolf | 2015-01-31 | 1 | -4/+4 | |
| | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |