aboutsummaryrefslogtreecommitdiffstats
path: root/backends
Commit message (Collapse)AuthorAgeFilesLines
...
* | Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_idMiodrag Milanović2022-03-042-4/+12
|\ \ | | | | | | add argument for printing cell names in yosys-smtbmc
| * | print cell name for properties in yosys-smtbmcN. Engelhardt2022-02-222-4/+12
| |/
* | Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-041-1/+16
|\ \ | | | | | | fix handling of escaped chars in json backend and frontend (mostly)
| * | fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-181-1/+16
| |/
* / Add a bit of flexibilty re trace length when processing aiger witnesses in ↵Claire Xenia Wolf2022-02-111-1/+4
|/ | | | | | smtbmc.py Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* verilog backend: Emit a `wire` for ports as well.Marcelina Kościelnicka2022-01-311-1/+1
| | | | Fixes #3177.
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-287-2/+77
|
* cxxrtl: don't reset elided wires with \init attribute.Catherine2021-12-251-0/+2
|
* cxxrtl: demote wires not inlinable only in debug_eval to locals.Catherine2021-12-151-3/+4
| | | | | | Fixes #3112. Co-authored-by: Irides <irides@irides.network>
* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-121-0/+2
| | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.
* Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2Catherine2021-12-122-108/+80
|\ | | | | cxxrtl: preserve interior memory pointers across reset
| * cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-112-95/+67
| | | | | | | | | | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer.
| * cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
| | | | | | | | This makes the depth properly immutable.
* | rtlil: Dump empty connections when whole module is selected.Marcelina Kościelnicka2021-12-121-2/+2
| | | | | | | | | | Without this, empty connections will be always skipped by `dump`, since they contain no selected wires. This makes debugging rather confusing.
* | write_verilog: dump zero width sigspecs correctly.whitequark2021-12-111-1/+2
|/ | | | | | | | | | | | | Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way.
* sta: very crude static timing analysis passLofty2021-11-251-15/+16
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Give initial wire unique ID, fixes #2914Miodrag Milanovic2021-11-171-4/+6
|
* Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
|
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-024-4/+19
|
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-43/+70
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* Add optimization to rtlil back-end for all-x parameter valuesClaire Xenia Wolf2021-09-271-9/+13
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix protobuf backend build dependenciesthe6p4c2021-09-171-0/+2
| | | | | | | backends/protobuf/protobuf.cc depends on the source and header files generated by protoc, but this dependency wasn't explicitly declared. Add a rule to the Makefile to fix intermittent build failures when the protobuf header/source file isn't built before protobuf.cc.
* yosys-smtbmc: Fix reused loop variable.Marcelina Kościelnicka2021-09-101-4/+4
| | | | Fixes #2999.
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-112-27/+30
|
* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
| | | | | | This mode will be used whenever read port cannot be handled in the "extract address register" way, ie. whenever it has enable, reset, init functionality or (in the future) mixed transparency mask.
* backends/verilog: Support meminit with mask.Marcelina Kościelnicka2021-07-281-3/+18
|
* Merge pull request #2885 from whitequark/cxxrtl-fix-2883whitequark2021-07-201-2/+8
|\ | | | | cxxrtl: treat wires with multiple defs as not inlinable
| * cxxrtl: treat wires with multiple defs as not inlinable.whitequark2021-07-201-2/+8
| | | | | | | | Fixes #2883.
* | cxxrtl: treat assignable internal wires used only for debug as locals.whitequark2021-07-201-10/+12
|/ | | | | | This issue was introduced in commit 4aa65f40 while fixing #2739. Fixes #2882.
* cxxrtl: escape colon in variable names in VCD writer.whitequark2021-07-191-1/+14
| | | | | | | | | | | | The following VCD file crashes GTKWave's VCD loader: $var wire 1 ! x:1 $end $enddefinitions $end In practice, a colon can be a part of a variable name that is translated from a Verilog function, something like: update$func$.../hdl/hazard3_csr.v:350$2534.$result
* cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
| | | | Fixes #2877.
* cxxrtl: treat internal wires used only for debug as constants.whitequark2021-07-171-0/+6
| | | | Fixes #2739 (again).
* Merge pull request #2874 from whitequark/cxxrtl-fix-2589whitequark2021-07-161-9/+6
|\ | | | | cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
| * cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.whitequark2021-07-161-9/+6
| | | | | | | | | | | | | | The hierarchy pass does a lot more than just finding the top module, mainly resolving implicit (positional, wildcard) module connections. Fixes #2589.
* | Merge pull request #2873 from whitequark/cxxrtl-fix-2500whitequark2021-07-161-3/+3
|\ \ | | | | | | cxxrtl: emit debug items for unused public wires
| * | cxxrtl: emit debug items for unused public wires.whitequark2021-07-161-3/+3
| |/ | | | | | | | | | | This greatly improves debug information coverage. Fixes #2500.
* / cxxrtl: don't expect user cell inputs to be wires.whitequark2021-07-161-2/+2
|/ | | | | | Ports can be connected to constants, too. (Usually resets.) Fixes #2521.
* cxxrtl: don't mark buffered internal wires as UNUSED for debug.whitequark2021-07-161-1/+1
| | | | | | | | | | Public wires may alias buffered internal wires, so keep BUFFERED wires in debug information even if they are private. Debug items are only created for public wires, so this does not otherwise affect how debug information is emitted. Fixes #2540. Fixes #2841.
* cxxrtl: mark dead local wires as unused even with inlining disabled.whitequark2021-07-151-4/+6
| | | | Fixes #2739.
* kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-131-1/+5
| | | | | | | While this helper is already useful to squash sequential initializations into one in cxxrtl, its main purpose is to squash overlapping masked memory initializations (when they land) and avoid having to deal with them in cxxrtl runtime.
* Add support for the Bitwuzla solverGCHQDeveloper5602021-07-121-5/+5
|
* cxxrtl: Support memory writes in processes.Marcelina Kościelnicka2021-07-121-6/+55
|
* cxxrtl: Add support for memory read port reset.Marcelina Kościelnicka2021-07-121-1/+41
|
* cxxrtl: Add support for mem read port initial data.Marcelina Kościelnicka2021-07-121-4/+22
|
* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
| | | | | This *only* does conversion, but doesn't add any new functionality — support for memory read port init/reset is still upcoming.
* Intersynth URLClaire Xenia Wolf2021-06-091-1/+1
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0819-20/+20
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-283-19/+6
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
|
* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 18:35:15 +0000