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* | Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_idMiodrag Milanović2022-03-042-4/+12
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| * | print cell name for properties in yosys-smtbmcN. Engelhardt2022-02-222-4/+12
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* | Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-041-1/+16
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| * | fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-181-1/+16
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* / Add a bit of flexibilty re trace length when processing aiger witnesses in sm...Claire Xenia Wolf2022-02-111-1/+4
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* verilog backend: Emit a `wire` for ports as well.Marcelina Kościelnicka2022-01-311-1/+1
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-287-2/+77
* cxxrtl: don't reset elided wires with \init attribute.Catherine2021-12-251-0/+2
* cxxrtl: demote wires not inlinable only in debug_eval to locals.Catherine2021-12-151-3/+4
* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-121-0/+2
* Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2Catherine2021-12-122-108/+80
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| * cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-112-95/+67
| * cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
* | rtlil: Dump empty connections when whole module is selected.Marcelina Kościelnicka2021-12-121-2/+2
* | write_verilog: dump zero width sigspecs correctly.whitequark2021-12-111-1/+2
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* sta: very crude static timing analysis passLofty2021-11-251-15/+16
* Give initial wire unique ID, fixes #2914Miodrag Milanovic2021-11-171-4/+6
* Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-024-4/+19
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-43/+70
* Add optimization to rtlil back-end for all-x parameter valuesClaire Xenia Wolf2021-09-271-9/+13
* Fix protobuf backend build dependenciesthe6p4c2021-09-171-0/+2
* yosys-smtbmc: Fix reused loop variable.Marcelina Kościelnicka2021-09-101-4/+4
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-112-27/+30
* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
* backends/verilog: Support meminit with mask.Marcelina Kościelnicka2021-07-281-3/+18
* Merge pull request #2885 from whitequark/cxxrtl-fix-2883whitequark2021-07-201-2/+8
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| * cxxrtl: treat wires with multiple defs as not inlinable.whitequark2021-07-201-2/+8
* | cxxrtl: treat assignable internal wires used only for debug as locals.whitequark2021-07-201-10/+12
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* cxxrtl: escape colon in variable names in VCD writer.whitequark2021-07-191-1/+14
* cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
* cxxrtl: treat internal wires used only for debug as constants.whitequark2021-07-171-0/+6
* Merge pull request #2874 from whitequark/cxxrtl-fix-2589whitequark2021-07-161-9/+6
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| * cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.whitequark2021-07-161-9/+6
* | Merge pull request #2873 from whitequark/cxxrtl-fix-2500whitequark2021-07-161-3/+3
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| * | cxxrtl: emit debug items for unused public wires.whitequark2021-07-161-3/+3
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* / cxxrtl: don't expect user cell inputs to be wires.whitequark2021-07-161-2/+2
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* cxxrtl: don't mark buffered internal wires as UNUSED for debug.whitequark2021-07-161-1/+1
* cxxrtl: mark dead local wires as unused even with inlining disabled.whitequark2021-07-151-4/+6
* kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-131-1/+5
* Add support for the Bitwuzla solverGCHQDeveloper5602021-07-121-5/+5
* cxxrtl: Support memory writes in processes.Marcelina Kościelnicka2021-07-121-6/+55
* cxxrtl: Add support for memory read port reset.Marcelina Kościelnicka2021-07-121-1/+41
* cxxrtl: Add support for mem read port initial data.Marcelina Kościelnicka2021-07-121-4/+22
* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
* Intersynth URLClaire Xenia Wolf2021-06-091-1/+1
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0819-20/+20
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-283-19/+6
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
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