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| * Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-211-21/+27
| * Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-211-2/+4
| * Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-211-17/+65
* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-181-8/+27
* | added $pmux cell translationAhmed Irfan2014-09-021-2/+38
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* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-122-6/+6
* disabling splice command in the scriptAhmed Irfan2014-02-112-2/+6
* register output correctedAhmed Irfan2014-02-111-1/+1
* added concat and slice cell translationAhmed Irfan2014-02-113-36/+59
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+22
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-061-1/+1
* Added BTOR backend README fileClifford Wolf2014-02-052-1/+24
* Added support for dump -appendClifford Wolf2014-02-041-3/+12
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-032-1/+6
* Merge branch 'btor' of https://github.com/ahmedirfan1983/yosysClifford Wolf2014-01-261-1/+5
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| * root bug correctedAhmed Irfan2014-01-251-1/+5
* | beautified write_intersynthJohann Glaser2014-01-251-0/+9
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* removed regex includeAhmed Irfan2014-01-241-1/+0
* merged clifford changes + removed regexAhmed Irfan2014-01-241-26/+52
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-242-2/+2
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-242-0/+50
* slice bug correctedAhmed Irfan2014-01-201-1/+1
* assert featureAhmed Irfan2014-01-201-9/+40
* verilog default options pullAhmed Irfan2014-01-171-28/+97
* slice error correctedAhmed Irfan2014-01-161-5/+5
* width issuesAhmed Irfan2014-01-151-64/+87
* BTOR backendAhmed Irfan2014-01-141-274/+328
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-032-7/+9
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| * Updated manual/command-reference-manual.texClifford Wolf2013-12-281-1/+1
| * Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-6/+8
* | btorAhmed Irfan2014-01-032-0/+774
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-042-2/+2
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-043-18/+24
* Fixed gentb_constant handling in autotest backendClifford Wolf2013-12-041-2/+2
* Added dump -m and -n optionsClifford Wolf2013-11-292-54/+89
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-241-4/+6
* Added support for signed parameters in ilangClifford Wolf2013-11-241-1/+1
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-241-2/+0
* Added modelsim support to autotestClifford Wolf2013-11-241-6/+6
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-243-0/+15
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-225-14/+14
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-211-1/+44
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-211-0/+1
* Silenced a gcc warning in spice backendClifford Wolf2013-11-091-1/+1
* Improved comments on topological sort in edif backendClifford Wolf2013-11-041-3/+4
* Added simple topological sort to edif backendClifford Wolf2013-11-031-2/+30
* Write yosys version to output filesClifford Wolf2013-11-035-6/+10
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-031-3/+5
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| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-031-3/+5
* | Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-311-1/+1
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