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* Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
|\ | | | | cxxrtl: do not use `->template` for non-dependent names
| * cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
| | | | | | | | This breaks build on MSVC but not GCC/Clang.
* | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
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* | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
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* add buffer option to spice backendPepijn de Vos2021-01-131-7/+15
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* cxxrtl: don't crash generating debug information for unused wires.whitequark2020-12-221-9/+10
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* cxxrtl: split processes into sync and case nodes.whitequark2020-12-221-11/+26
| | | | | | | | | | | Similar to the treatment of black boxes, splitting processes into two scheduling nodes adds sufficient freedom so that netlists with well-behaved processes (e.g. those emitted by nMigen) can immediately converge. Because processes are not emitted into edge-triggered regions, this approach has comparable performance to -O5 (without -noproc), which is substantially slower than -O6.
* cxxrtl: completely rewrite netlist layout code.whitequark2020-12-221-406/+569
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exact shape of C++ code emitted by CXXRTL has a critical effect on performance, both compile-time and runtime. CXXRTL's performance greatly improved when it started localizing and inlining wires, not only because this assists the optimizer and register allocator, but also because inlining code into edge-triggered regions cuts the time spent in eval() by at least a factor of two. However, the logic of netlist layout has always been ad-hoc, fragile, and very hard to understand and modify. After commit ece25a45, which introduced outlining, the same logic started being applied to two distinct netlists at once instead of one, which barely worked. This commit does four major changes: * There is now a single unambiguous source of truth (per subgraph) for the layout of any emitted wire. * Netlist layout is now done entirely during analysis using well known graph algorithms; no graph operations happen when emitting. * Netlist layout now happens completely separately for eval() and debug_eval() subgraphs. * Unreachable (within subgraph scope) netlist nodes are now neither emitted nor considered for wire inlining decisions. The netlist layout code should also now closely match the described semantics. As a part of this large cleanup, it includes many miscellaneous improvements: * The "bare minimum" debug level introduced in commit dd6a761d was split into two levels; -g1 now emits debug information *only* for inputs and state wires, and -g2 now emits debug information for all public members. The old behavior matches -g2. This is done to avoid bloat on low optimization levels. * Debug aliases and inlined connections are now handled separately, and complex RHS never interferes with inlined connections. * Aliases to outlined wires now carry a pointer to the outline. * Cell sync outputs can now be emitted in debug_eval(). * Black box debug information now includes comb/sync driver flags. * The comment emitted for inlined cells is now accurate. * Debug information statistics now has less noise. * Netlist layout code is now much better documented. Due to more precise inlining decisions, unmodified (i.e. with no Yosys script being used) netlists now have much more logic inlined into edge-triggered regions. On Minerva SoC SRAM, this improves runtime by 20-25% across compilers and optimization levels. Due to more precise reachability analysis, much less C++ code is now emitted, especially at the maximum debug level. On Minerva SoC SRAM, this improves clang compile time by 30-50% depending on options. gcc is not affected.
* cxxrtl: simplify logic choosing wire type. NFCI.whitequark2020-12-211-19/+8
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* cxxrtl: clarify node use-def construction. NFCI.whitequark2020-12-211-18/+11
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* cxxrtl: fix typo.whitequark2020-12-211-2/+2
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* cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-212-5/+28
| | | | | On Minerva SoC SRAM, depending on the compiler, this change improves overall time by 4-7%.
* cxxrtl: speed up commits on clang.whitequark2020-12-211-3/+3
| | | | | | On Minerva SoC SRAM compiled with clang-11, this change cuts commit time in half (!) and overall time by 20%. When compiled with gcc-10, there is no difference.
* cxxrtl: use `static inline` instead of `inline` in the C API.whitequark2020-12-201-1/+1
| | | | | | In C, non-static inline functions require an implementation elsewhere (even though the body is right there in the header). It is basically never desirable to use those as opposed to static inline ones.
* cxxrtl: print names of cells inlined in connections.whitequark2020-12-151-1/+10
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* cxxrtl: disable optimization of debug_items().whitequark2020-12-152-3/+15
| | | | | | | | | | | | | | | | | | Implementing outlining has greatly increased the amount of debug information in a typical build, and consequently exposed performance issues in C++ compilers, which are similar for both GCC and Clang; the compile time of Minerva SoC SRAM increased almost twofold. Although one would expect the slowdown to be caused by the increased use of templates in `debug_eval()`, it is actually almost entirely attributable to optimizations and codegen for `debug_items()`. Fortunately, it is neither possible nor desirable to optimize `debug_items()`: in most cases it is called exactly once, and its body is a linear sequence of calls with unique arguments. This commit turns off optimizations for `debug_items()` on GCC and Clang, improving -Os compile time of Minerva SoC SRAM by ~40% (!)
* cxxrtl: make alias analysis outlining-aware.whitequark2020-12-151-38/+48
| | | | | | | | | | | | | | | | | | Before this commit, if a sequence of wires assigned in a chain would terminate on a cell, none of the wires would get marked as aliases, and typically all of the public wires would get outlined. The reason for this behavior is that alias analysis predates outlining and in fact runs before it. After this commit, alias analysis runs after outlining and considers outlined wires valid aliasees. More importantly, if the chained wires contain any valid aliasees, then all of the wires are aliased to the one that is topologically deepest. Aliased wires incur virtually no overhead for the VCD writer, unlike outlined wires that would otherwise take their place. On Minerva SoC SRAM, size of the full VCD dump is reduced by ~65%, and throughput is increased by ~55%.
* cxxrtl: add a "bare minimum" debug information level.whitequark2020-12-141-9/+17
| | | | | Useful to reduce overhead when no debug capabilities are necessary except for access to design state.
* cxxrtl: implement debug information outlining.whitequark2020-12-145-71/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aggressive wire localization and inlining is necessary for CXXRTL to achieve high performance. However, that comes with a cost: reduced debug information coverage. Previously, as a workaround, the `-Og` option could have been used to guarantee complete coverage, at a cost of a significant performance penalty. This commit introduces debug information outlining. The main eval() function is compiled with the user-specified optimization settings. In tandem, an auxiliary debug_eval() function, compiled from the same netlist, can be used to reconstruct the values of localized/inlined signals on demand. To the extent that it is possible, debug_eval() reuses the results of computations performed by eval(), only filling in the missing values. Benchmarking a representative design (Minerva SoC SRAM) shows that: * Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%. * Switching from `-g1` to `-g2`, both used with `-O6`, increases compile time by ~25%. * Although `-g2` increases the resident size of generated modules, this has no effect on runtime. Because the impact of `-g2` is minimal and the benefits of having unconditional 100% debug information coverage (and the performance improvement as well) are major, this commit removes `-Og` and changes the defaults to `-O6 -g2`. We'll have our cake and eat it too!
* cxxrtl: rename "elision" to "inlining". NFC.whitequark2020-12-131-77/+77
| | | | | | | "Elision" in this context is an unusual and not very descriptive term whereas "inlining" is common and straightforward. Also, introducing "inlining" makes it easier to introduce its dual under the obvious name "outlining".
* cxxrtl: fix outdated comment. NFC.whitequark2020-12-131-2/+2
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* cxxrtl: use IdString::isPublic(). NFC.whitequark2020-12-131-4/+4
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* cxxrtl: don't overwrite buffered inputs.whitequark2020-12-112-25/+33
| | | | | | | | | | | | | | Before this commit, a cell's input was always assigned like: p_cell.p_input = (value...); If `p_input` is buffered (e.g. if the design is built at -O0), this is not correct. (In practice, this breaks clocking.) Unfortunately, the incorrect design was compiled without diagnostics because wire<> was move-assignable and also implicitly constructible from value<>. After this commit, cell inputs are no longer incorrectly assumed to always be unbuffered, and wires are not assignable from values.
* cxxrtl: allow customizing the root module path in the C API.whitequark2020-12-032-1/+20
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* Merge pull request #2468 from whitequark/cxxrtl-assertwhitequark2020-12-022-2/+16
|\ | | | | cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert
| * cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert.whitequark2020-12-022-2/+16
| | | | | | | | | | | | | | | | RTL contract violations and C++ contract violations are different: the former depend on the netlist and will never violate memory safety whereas the latter may. When loading a CXXRTL simulation into another process, RTL contract violations should generally not crash it, while C++ contract violations should.
* | Merge pull request #2469 from whitequark/cxxrtl-no-clkwhitequark2020-12-021-6/+14
|\ \ | | | | | | cxxrtl: fix crashes caused by a floating or constant clock input
| * | cxxrtl: fix crashes caused by a floating or constant clock input.whitequark2020-12-021-6/+14
| |/ | | | | | | | | | | | | | | | | | | | | E.g. in: module test; wire clk = 0; reg data; always @(posedge clk) data <= 0; endmodule
* / cxxrtl: provide a way to perform unobtrusive power-on reset.whitequark2020-12-024-3/+78
|/ | | | | | | | | | | Although it is always possible to destroy and recreate the design to simulate a power-on reset, this has two drawbacks: * Black boxes are also destroyed and recreated, which causes them to reacquire their resources, which might be costly and/or erase important state. * Pointers into the design are invalidated and have to be acquired again, which is costly and might be very inconvenient if they are captured elsewhere (especially through the C API).
* Add verilog backend option for simple_lhsMiodrag Milanovic2020-11-251-6/+22
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* generate only simple assignments in verilog backendMiodrag Milanovic2020-11-251-5/+9
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* Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parametersMiodrag Milanović2020-11-241-58/+294
|\ | | | | Add firrtl backend support for generic parameters in blackbox components
| * Formatting fixesSahand Kashani2020-11-231-10/+7
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| * Add support for real-valued parameters + preserve type of parametersSahand Kashani2020-08-061-38/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for real-valued parameters in blackboxes. Additionally, parameters now retain their types are no longer all encoded as strings. There is a caveat with this implementation due to my limited knowledge of yosys, more specifically to how yosys encodes bitwidths of parameter values. The example below can motivate the implementation choice I took. Suppose a verilog component is declared with the following parameters: parameter signed [26:0] test_signed; parameter [26:0] test_unsigned; parameter signed [40:0] test_signed_large; If you instantiate it as follows: defparam <inst_name> .test_signed = 49; defparam <inst_name> .test_unsigned = 40'd35; defparam <inst_name> .test_signed_large = 40'd12; If you peek in the RTLIL::Const structure corresponding to these params, you realize that parameter "test_signed" is being considered as a 32-bit value since it's declared as "49" without a width specifier, even though the parameter is defined to have a maximum width of 27 bits. A similar issue occurs for parameter "test_unsigned" where it is supposed to take a maximum bit width of 27 bits, but if the user supplies a 40-bit value as above, then yosys considers the value to be 40 bits. I suppose this is due to the type being defined by the RHS rather than the definition. Regardless of this, I emit the same widths as what the user specifies on the RHS when generating firrtl IR.
| * Add firrtl backend support for generic parameters in blackbox componentsSahand Kashani2020-07-231-58/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous blackbox components were just emitted with their interface ports, but their generic parameters were never emitted and it was therefore impossible to customize them. This commit adds support for blackbox generic parameters, though support is only provided for INTEGER and STRING parameters. Other types of parameters such as DOUBLEs, ..., would result in undefined behavior here. This allows the emission of custom extmodule instances such as the following: extmodule fourteennm_lcell_comb_<instName>: input cin: UInt<1> output combout: UInt<1> output cout: UInt<1> input dataa: UInt<1> input datab: UInt<1> input datac: UInt<1> input datad: UInt<1> input datae: UInt<1> input dataf: UInt<1> input datag: UInt<1> input datah: UInt<1> input sharein: UInt<1> output shareout: UInt<1> output sumout: UInt<1> defname = fourteennm_lcell_comb parameter extended_lut = "off" parameter lut_mask = "b0001001000010010000100100001001000010010000100100001001000010010" parameter shared_arith = "off"
* | backends/blif: Remove unused vector of strings (#2420)William Woodruff2020-11-161-57/+53
| | | | | | | | | | | | | | | | | | | | | | * backends/blif: Remove unused vector of strings For reasons that are unclear to me, this was being used to store every result of `cstr` before returning them. The vector was never accessed otherwise, resulting in a huge unnecessary memory sink when emitting to BLIF. * backends/blif: Remove CSTR macro * backends/blif: Actually call str()
* | cxxrtl: run `hierarchy -auto-top` if no top module is present.whitequark2020-11-021-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | In most cases, a CXXRTL simulation would use a top module, either because this module serves as an entry point to the CXXRTL C API, or because the outputs of a top module are unbuffered, improving performance. Taking this into account, the CXXRTL backend now runs `hierarchy -auto-top` if there is no top module. For the few cases where this behavior is unwanted, it now accepts a `-nohierarchy` option. Fixes #2373.
* | cxxrtl: don't assert on non-constant $meminit inputs.whitequark2020-11-011-2/+4
| | | | | | | | Fixes #2129.
* | cxxrtl: don't assert on wires with multiple drivers.whitequark2020-11-011-0/+2
| | | | | | | | Fixes #2374.
* | btor: Use Mem helper.Marcelina Kościelnicka2020-10-211-93/+102
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* | smt2: Use Mem helper.Marcelina Kościelnicka2020-10-211-186/+244
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* | verilog_backend: Use Mem helper.Marcelina Kościelnicka2020-10-211-274/+251
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* | smtbmc: escape identifiers in verilog testbenchJakob Wenzel2020-10-061-11/+29
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* | write_verilog: emit intermediate wire for constant values in sensitivity listN. Engelhardt2020-09-281-7/+53
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* | Merge pull request #2372 from nakengelhardt/name_is_publicN. Engelhardt2020-09-214-8/+8
|\ \ | | | | | | add IdString::isPublic()
| * | use the new isPublic() in a few placesN. Engelhardt2020-09-144-8/+8
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* | | Merge pull request #2369 from Xiretza/gitignoresMiodrag Milanović2020-09-102-0/+2
|\ \ \ | |/ / |/| | Add missing gitignores for test artifacts
| * | Add missing gitignores for test artifactsXiretza2020-08-312-0/+2
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* | | cxxrtl: expose driver kind in debug information.whitequark2020-09-023-12/+112
| | | | | | | | | | | | | | | | | | This can be useful to determine whether the wire should be a part of a design checkpoint, whether it can be used to override design state, and whether driving it may cause a conflict.
* | | cxxrtl: improve handling of FFs with async inputs (other than CLK).whitequark2020-09-021-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, the meaning of "sync def" included some flip-flop cells but not others. There was no actual reason for this; it was just poorly defined. After this commit, a "sync def" means that a wire holds design state because it is connected directly to a flip-flop output, and may never be unbuffered. This is not affected by presence of async inputs.
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