iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-4/+4
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-2/+2
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-4/+4
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-43/+43
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-43/+43
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*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-21/+29
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-3/+0
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-2/+2
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-29/+29
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-29/+29
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*	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog ↵	Clifford Wolf	2014-07-20	1	-17/+21
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*	Added support for $bu0 to verilog backend	Clifford Wolf	2014-07-20	1	-0/+16
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+22
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-6/+8
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-8/+11
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*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24	1	-4/+6
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-7/+7
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*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21	1	-1/+44
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*	Write yosys version to output files	Clifford Wolf	2013-11-03	1	-2/+2
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*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-1/+1
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*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	1	-4/+4
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*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	1	-0/+1
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*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-28/+1
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*	Added -selected option to various backends	Clifford Wolf	2013-09-03	1	-6/+21
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*	More explicit integer output in verilog backend	Clifford Wolf	2013-08-22	1	-2/+2
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-6/+18
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*	Avoid verilog-2k in verilog backend	Clifford Wolf	2013-03-21	1	-0/+17
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*	More support code for $sr cells	Clifford Wolf	2013-03-14	1	-1/+29
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*	Fixed a gcc compiler warning [-Wparentheses]	Clifford Wolf	2013-03-03	1	-1/+2
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*	Added more help messages	Clifford Wolf	2013-03-01	1	-1/+25
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+905