iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-1/+1
\|
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-10/+6
\|
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-2/+0
\|
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-12/+12
\|
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-12/+12
\|
*	beautified write_intersynth	Johann Glaser	2014-01-25	1	-0/+9
\|
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
\|
*	Ignore explicit unconnected ports in intersynth backend	Clifford Wolf	2013-11-03	1	-3/+5
\|
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-1/+1
\|
*	Added -selected option to various backends	Clifford Wolf	2013-09-03	1	-0/+17
\|
*	Added -notypes option to intersynth backend	Clifford Wolf	2013-03-24	1	-7/+18
\|
*	Fixed gcc build (intersynth backend)	Clifford Wolf	2013-03-23	1	-14/+14
\|
*	Various improvements in intersynth backend	Clifford Wolf	2013-03-23	1	-9/+56
\|
*	Added intersynth backend	Clifford Wolf	2013-03-23	1	-0/+138