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* More progress on Firrtl backend.Adam Izraelevitz2017-02-131-5/+117
| | | | | Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
* Bugfix: include assign to write-maskAdam Izraelevitz2016-11-181-0/+1
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* More progress in FIRRTL back-endClifford Wolf2016-11-181-0/+96
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* Progress in FIRRTL back-endClifford Wolf2016-11-181-5/+28
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* Added first draft of FIRRTL back-endClifford Wolf2016-11-171-0/+350