| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | More progress on Firrtl backend. | Adam Izraelevitz | 2017-02-13 | 1 | -5/+117 |
| | | | | | | Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design. | ||||
| * | Bugfix: include assign to write-mask | Adam Izraelevitz | 2016-11-18 | 1 | -0/+1 |
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| * | More progress in FIRRTL back-end | Clifford Wolf | 2016-11-18 | 1 | -0/+96 |
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| * | Progress in FIRRTL back-end | Clifford Wolf | 2016-11-18 | 1 | -5/+28 |
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| * | Added first draft of FIRRTL back-end | Clifford Wolf | 2016-11-17 | 1 | -0/+350 |
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index : iCE40/yosys | |
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