iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
\|
*	Fixed some typos	Clifford Wolf	2016-04-05	1	-1/+1
\|
*	Added "write_edif -nogndvcc"	Clifford Wolf	2016-03-08	1	-17/+34
\|
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
\|
*	Added EDIF backend support for multi-bit cell ports	Clifford Wolf	2015-02-01	1	-11/+10
\|
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
\|
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
\|
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-69/+69
\|
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-2/+2
\|
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
\|
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
\|
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-6/+6
\|
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
\|
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
\|
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-2/+2
\|
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-9/+6
\|
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
\|
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-6/+3
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
\|
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-10/+10
\|
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-10/+10
\|
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21	1	-21/+27
\|
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21	1	-2/+4
\|
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-2/+2
\|
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	1	-0/+5
\|
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-3/+3
\|
*	Improved comments on topological sort in edif backend	Clifford Wolf	2013-11-04	1	-3/+4
\|
*	Added simple topological sort to edif backend	Clifford Wolf	2013-11-03	1	-2/+30
\|
*	Write yosys version to output files	Clifford Wolf	2013-11-03	1	-0/+4
\|
*	Fixed hex string generation bug in edif backend	Clifford Wolf	2013-10-27	1	-4/+4
\|
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-3/+3
\|
*	Improvements in EDIF backend	Clifford Wolf	2013-09-17	1	-1/+40
\|
*	Encode large (>32 bits) parameters as hex string in edif backend	Clifford Wolf	2013-08-28	1	-3/+16
\|
*	Improved edif backend	Clifford Wolf	2013-08-27	1	-8/+18
\|
*	Added correct encoding of identifiers in EDIF backend	Clifford Wolf	2013-08-22	1	-13/+61
\|
*	Added edif backend (still under construction)	Clifford Wolf	2013-08-22	2	-0/+202