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* cxxrtl: use one delta cycle for immediately converging netlists.whitequark2020-04-211-3/+4
| | | | | | | | | | | If it is statically known that eval() will converge in one delta cycle (that is, the second commit() will always return `false`) because the design contains no feedback or buffered wires, then there is no need to run the second delta cycle at all. After this commit, the case where eval() always converges immediately is detected and the second delta cycle is omitted. As a result, Minerva SRAM SoC runs ~25% faster.
* cxxrtl: provide attributes to black box factories, too.whitequark2020-04-191-10/+10
| | | | | | | | | Both parameters and attributes are necessary because the parameters have to be the same between every instantiation of the cell, but attributes may well vary. For example, for an UART PHY, the type of the PHY (tty, pty, socket) would be a parameter, but configuration of the implementation specified by the type (socket address) would be an attribute.
* cxxrtl: add simple black box support.whitequark2020-04-181-0/+53
| | | | | | | This commit adds support for replacing RTLIL modules with CXXRTL black boxes. Black box port widths may not depend on the parameters with which it is instantiated (yet); the parameters may only be used to change the behavior of the black box.
* cxxrtl: make ROMs writable, document memory::operator[].whitequark2020-04-161-2/+5
| | | | | | | | | | | There is no practical benefit from using `const memory` for ROMs; it uses an std::vector internally, which prevents contemporary compilers from constant-propagating ROM contents. (It is not clear whether they are permitted to do so.) However, there is a major benefit from using non-const `memory` for ROMs, which is the ability to dynamically fill the ROM for each individual simulation.
* write_cxxrtl: improve writable memory handling.whitequark2020-04-091-39/+64
| | | | | | This commit reduces space and time overhead for writable memories to O(write port count) in both cases; implements handling for write port priorities; and simplifies runtime representation of memories.
* write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.whitequark2020-04-091-8/+13
| | | | | | | | | | After this commit, if NDEBUG is not defined, out-of-bounds accesses cause assertion failures for reads and writes. If NDEBUG is defined, out-of-bounds reads return zeroes, and out-of-bounds writes are ignored. This commit also adds support for memories that start with a non-zero index (`Memory::start_offset` in RTLIL).
* write_cxxrtl: statically schedule comb logic and localize wires.whitequark2020-04-091-0/+4
| | | | | | This results in further massive gains in performance, modest decrease in compile time, and, for designs without feedback arcs, makes it possible to run eval() once per clock edge in certain conditions.
* write_cxxrtl: new backend.whitequark2020-04-091-0/+1104
This commit adds a basic implementation that isn't very performant but implements most of the planned features.