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| * Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
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| * Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-2/+2
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| * More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-34/+34
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| * Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
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| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-34/+34
| | | | | | | | | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-34/+34
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| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-251-21/+21
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| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-2/+2
| | | | | | | | created interim RTLIL::SigSpec::chunks_rw()
| * SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-40/+40
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| * SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-40/+40
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| * Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-071-18/+17
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* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-181-8/+27
| | | | | | | | fixed reduce_xnor, logic_not bug translation bug
* | added $pmux cell translationAhmed Irfan2014-09-021-2/+38
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* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-122-6/+6
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* disabling splice command in the scriptAhmed Irfan2014-02-112-2/+6
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* register output correctedAhmed Irfan2014-02-111-1/+1
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* added concat and slice cell translationAhmed Irfan2014-02-113-36/+59
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* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-061-1/+1
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* Added BTOR backend README fileClifford Wolf2014-02-052-1/+24
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-032-1/+6
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* root bug correctedAhmed Irfan2014-01-251-1/+5
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* removed regex includeAhmed Irfan2014-01-241-1/+0
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* merged clifford changes + removed regexAhmed Irfan2014-01-241-26/+52
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* Use techmap -share_map in btor scriptsClifford Wolf2014-01-242-2/+2
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* Moved btor scripts to backends/btor/Clifford Wolf2014-01-242-0/+50
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* slice bug correctedAhmed Irfan2014-01-201-1/+1
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* assert featureAhmed Irfan2014-01-201-9/+40
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* verilog default options pullAhmed Irfan2014-01-171-28/+97
| | | | shift operator width issues
* slice error correctedAhmed Irfan2014-01-161-5/+5
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* width issuesAhmed Irfan2014-01-151-64/+87
| | | | dff cell for more than one registers
* BTOR backendAhmed Irfan2014-01-141-274/+328
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* btorAhmed Irfan2014-01-032-0/+774
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