iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
*	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07	1	-18/+17
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*	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12	2	-6/+6
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*	disabling splice command in the script	Ahmed Irfan	2014-02-11	2	-2/+6
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*	register output corrected	Ahmed Irfan	2014-02-11	1	-1/+1
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*	added concat and slice cell translation	Ahmed Irfan	2014-02-11	3	-36/+59
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*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06	1	-1/+1
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*	Added BTOR backend README file	Clifford Wolf	2014-02-05	2	-1/+24
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	2	-1/+6
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*	root bug corrected	Ahmed Irfan	2014-01-25	1	-1/+5
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*	removed regex include	Ahmed Irfan	2014-01-24	1	-1/+0
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*	merged clifford changes + removed regex	Ahmed Irfan	2014-01-24	1	-26/+52
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*	Use techmap -share_map in btor scripts	Clifford Wolf	2014-01-24	2	-2/+2
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*	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24	2	-0/+50
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*	slice bug corrected	Ahmed Irfan	2014-01-20	1	-1/+1
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*	assert feature	Ahmed Irfan	2014-01-20	1	-9/+40
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*	verilog default options pull	Ahmed Irfan	2014-01-17	1	-28/+97
\| \| \| \|	shift operator width issues
*	slice error corrected	Ahmed Irfan	2014-01-16	1	-5/+5
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*	width issues	Ahmed Irfan	2014-01-15	1	-64/+87
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*	BTOR backend	Ahmed Irfan	2014-01-14	1	-274/+328
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*	btor	Ahmed Irfan	2014-01-03	2	-0/+774