| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | | | * | sv: Add test scripts for typedefs | David Shah | 2019-10-03 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys ↵ | Eddie Hung | 2019-09-30 | 1 | -0/+1 | |
| | | |\ \ \ | | | |_|/ | | |/| | | | | | | | into eddie/pr1352 | |||||
| | | | * | | Add tests for ECP5 architecture | SergeyDegtyar | 2019-09-03 | 1 | -0/+1 | |
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| | * | | | | Merge branch 'SergeyDegtyar/anlogic' of ↵ | Miodrag Milanovic | 2019-10-04 | 1 | -0/+1 | |
| | |\ \ \ \ | | |_|_|/ | |/| | | | | | | | | https://github.com/SergeyDegtyar/yosys into mmicko/anlogic | |||||
| | | * | | | Merge branch 'master' into SergeyDegtyar/anlogic | Sergey | 2019-10-01 | 1 | -4/+8 | |
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| | | * | | | Add new tests for Anlogic architecture | SergeyDegtyar | 2019-09-23 | 1 | -0/+1 | |
| | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. | |||||
| * | | | | Merge branch 'SergeyDegtyar/efinix' of ↵ | Miodrag Milanovic | 2019-10-04 | 1 | -0/+1 | |
| |\ \ \ \ | |/ / / |/| | | | | | | | https://github.com/SergeyDegtyar/yosys into mmicko/efinix | |||||
| | * | | | Merge branch 'master' into SergeyDegtyar/efinix | Sergey | 2019-10-01 | 1 | -4/+8 | |
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| | * | | | Add new tests for Efinix architecture. | SergeyDegtyar | 2019-09-23 | 1 | -0/+1 | |
| | | |/ | |/| | | | | | | | | | | | | | | | | Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. | |||||
| * | | | Update ABC to git rev 623b5e8 | Clifford Wolf | 2019-10-03 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Bump version | Clifford Wolf | 2019-10-03 | 1 | -1/+1 | |
| | |/ |/| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 1 | -0/+4 | |
| |\ \ | | | | | | | rpc: new frontend | |||||
| | * | | rpc: new frontend. | whitequark | 2019-09-30 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design. | |||||
| | * | | libs: import json11. | whitequark | 2019-09-30 | 1 | -0/+3 | |
| | | | | | | | | | | | | | | | | This commit imports the code from upstream commit dropbox/json11@8ccf1f0c5ecab6151a65f216e7eeccd8588e5457. | |||||
| * | | | Bump version | Clifford Wolf | 2019-09-30 | 1 | -1/+1 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Bump version | Clifford Wolf | 2019-09-16 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Bump version | Clifford Wolf | 2019-09-10 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Bump version | Clifford Wolf | 2019-09-05 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Use $(shell :; ...) in Makefile to force shell | Emily | 2019-09-05 | 1 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Did you think that `$(shell command -v ...)` would actually get run by the shell? Foolish mortal; GNU Make is obviously far more wise than thee, as it optimizes it to a direct -- and hence broken (since `command` is a shell builtin) -- exec. This horrifying contortion ensures that an actual shell runs the command and fixes the behaviour. @Shizmob found the source of this misbehaviour; turns out gmake has a hard-coded, incomplete list of shell builtins: https://github.com/mirror/make/blob/715c787dc69bac37827a7d6ea6d40a86c55b5583/src/job.c#L2691 This contains `command`, but the whole function is full of horrible heuristic garbage so who knows. I'm so sorry. | |||||
| * | | Replace `which` with `command -v` in Makefile too | Emily | 2019-09-04 | 1 | -3/+3 | |
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| * | Merge pull request #2 from YosysHQ/master | Sergey | 2019-08-29 | 1 | -1/+1 | |
| |\ | | | | | Pull from upstream | |||||
| | * | Bump YOSYS_VER | Clifford Wolf | 2019-08-29 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge remote-tracking branch 'origin/clifford/async2synclatch' into ↵ | Eddie Hung | 2019-08-28 | 1 | -1/+11 | |
| |\| | | | | | | | Sergey/tests_ice40 | |||||
| | * | Add "make bumpversion" | Clifford Wolf | 2019-08-27 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge tag 'yosys-0.9' | Clifford Wolf | 2019-08-26 | 1 | -1/+1 | |
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| | | * | Yosys 0.9 | Clifford Wolf | 2019-08-26 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 | |
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| | | * | Fix linking issue for new mxe and pthread | Miodrag Milanovic | 2019-08-02 | 1 | -1/+2 | |
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| | | * | Fix yosys linking for mxe | Miodrag Milanovic | 2019-08-02 | 1 | -1/+1 | |
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| | | * | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-02 | 1 | -0/+2 | |
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| | | * | Merge pull request #1146 from gsomlo/gls-test-abc-ext | Clifford Wolf | 2019-07-09 | 1 | -2/+8 | |
| | | | | | | | | | | tests: use optional ABCEXTERNAL when specified | |||||
| | | * | Checkout yosys-0.9-rc branch of yosys-tests | Eddie Hung | 2019-07-02 | 1 | -1/+1 | |
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| | * | | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 | |
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| | * | | Merge branch 'master' into clifford/pmgen | Clifford Wolf | 2019-08-20 | 1 | -0/+1 | |
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| | * \ \ | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen | Clifford Wolf | 2019-08-19 | 1 | -1/+2 | |
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| | * | | | | Improvements in pmgen for recursive patterns | Clifford Wolf | 2019-08-15 | 1 | -0/+5 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Revert "Add tests for ecp5" | SergeyDegtyar | 2019-08-28 | 1 | -1/+0 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 2270ead09fb4695442c66fe5c06445235f390f2b. | |||||
| * | | | | | Add tests for ecp5 | SergeyDegtyar | 2019-08-28 | 1 | -0/+1 | |
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| * | | | | | Revert "Add tests for ecp5 architecture." | SergeyDegtyar | 2019-08-27 | 1 | -1/+0 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 134d3fea909bae02f4f814e3d649658502b44b73. | |||||
| * | | | | | Add tests for ecp5 architecture. | SergeyDegtyar | 2019-08-27 | 1 | -0/+1 | |
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| * | | | | | Add new tests for ice40 architecture | SergeyDegtyar | 2019-08-20 | 1 | -0/+1 | |
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| * | | | | proc_clean: fix order of switch insertion. | whitequark | 2019-08-19 | 1 | -0/+1 | |
| | |/ / |/| | | | | | | | | Fixes #1268. | |||||
| * | | | Merge remote-tracking branch 'origin/master' into clifford/testfast | Eddie Hung | 2019-08-18 | 1 | -0/+1 | |
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| | * \ \ | Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share | Eddie Hung | 2019-08-16 | 1 | -0/+1 | |
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| | | * | | Support various binary operators in opt_share | Bogdan Vukobratovic | 2019-08-04 | 1 | -0/+1 | |
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| * | | | | Speed up "make test" and related cleanups | Clifford Wolf | 2019-08-17 | 1 | -1/+1 | |
| |/ / / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | 'make clean' to not remove anything abc | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
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| * | | | Fix linking issue for new mxe and pthread | Miodrag Milanovic | 2019-08-01 | 1 | -1/+2 | |
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| * | | | Fix yosys linking for mxe | Miodrag Milanovic | 2019-08-01 | 1 | -1/+1 | |
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| * | | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 1 | -0/+2 | |
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index : iCE40/yosys | |
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