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* Merge pull request #2117 from PeterCrozier/struct_arrayclairexen2020-06-083-17/+158
|\ | | | | Support packed arrays in struct/union.
| * Support packed arrays in struct/union.Peter Crozier2020-06-073-17/+158
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* | Merge pull request #2119 from YosysHQ/mwk/fix-fsm-idstringclairexen2020-06-081-1/+1
|\ \ | | | | | | fsm_extract: avoid calling log_signal to determine wire name
| * | fsm_extract: avoid calling log_signal to determine wire nameMarcelina Kościelnicka2020-06-081-1/+1
|/ / | | | | | | | | | | | | | | | | | | log_signal can result in a string with spaces (when bit selection is involved), which breaks the rule of IdString not containing whitespace. Instead, remove the sigspec from the name entirely — given that the resulting wire will have no users, it will be removed later anyway, so its name doesn't really matter. Fixes #2118
* | Merge pull request #2116 from whitequark/cxxrtl-vcdwhitequark2020-06-077-3/+419
|\ \ | |/ |/| cxxrtl: add a VCD writer using debug information
| * cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.whitequark2020-06-072-1/+1
| | | | | | | | | | To avoid confusion with the C++ source files that are a part of the simulation itself and not a part of Yosys build.
| * cxxrtl: add a C API for writing VCD dumps.whitequark2020-06-075-2/+204
| | | | | | | | This C API is fully featured.
| * cxxrtl: only write VCD values that were actually updated.whitequark2020-06-071-10/+30
| | | | | | | | | | On a representative design (Minerva SoC) this reduces VCD file size by ~20× and runtime by ~3×.
| * cxxrtl: add a VCD writer using debug information.whitequark2020-06-071-0/+194
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* Merge pull request #2115 from whitequark/cxxrtl-introspectionwhitequark2020-06-064-5/+396
|\ | | | | cxxrtl: add debug information to the C++ API, and add introspection via a new C API
| * cxxrtl: add a C API for driving and introspecting designs.whitequark2020-06-064-29/+291
| | | | | | | | | | | | Compared to the C++ API, the C API currently has two limitations: 1. Memories cannot be updated in a race-free way. 2. Black boxes cannot be implemented in C.
| * cxxrtl: generate debug information for non-localized public wires.whitequark2020-06-062-2/+131
|/ | | | | | | | | | Debug information describes values, wires, and memories with a simple C-compatible layout. It can be emitted on demand into a map, which has no runtime cost when it is unused, and allows late bound designs. The `hdlname` attribute is used as the lookup key such that original names, as emitted by the frontend, can be used for debugging and introspection.
* Merge pull request #2110 from BracketMaster/masterwhitequark2020-06-061-1/+1
|\ | | | | MacOS has even stricter stack limits in catalina.
| * more reasonable numbers for memoryYehowshua Immanuel2020-06-041-1/+1
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| * MacOS has even stricter stack limits in catalina.Yehowshua Immanuel2020-06-041-1/+1
| | | | | | Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
* | Merge pull request #2113 from whitequark/cxxrtl-fix-sshrwhitequark2020-06-051-1/+1
|\ \ | | | | | | cxxrtl: fix implementation of $sshr cell
| * | cxxrtl: fix implementation of $sshr cell.whitequark2020-06-051-1/+1
| | | | | | | | | | | | Fixes #2111.
* | | Merge pull request #2109 from nakengelhardt/btor_internal_namesN. Engelhardt2020-06-051-5/+5
|\ \ \ | | | | | | | | btor backend: make not printing internal names default
| * | | btor backend: make not printing internal names defaultN. Engelhardt2020-06-041-5/+5
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* | | | Add missing .gitignore fileClaire Wolf2020-06-041-0/+2
| |_|/ |/| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2041 from PeterCrozier/structclairexen2020-06-0410-204/+690
|\ \ \ | | | | | | | | Implementation of SV structs.
| * \ \ Merge branch 'master' into structPeter Crozier2020-06-03154-2453/+4094
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| * | | | Allow structs within structs.Peter Crozier2020-05-123-7/+38
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| * | | | Generalise structs and add support for packed unions.Peter Crozier2020-05-128-59/+209
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| * | | | Implement SV structs.Peter Crozier2020-05-089-205/+510
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* | | | | Merge pull request #2099 from Xiretza/manual-include-pathclairexen2020-06-041-1/+4
|\ \ \ \ \ | | | | | | | | | | | | Use in-tree include directory in manual build
| * | | | | Use in-tree include directory in manual buildXiretza2020-05-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is basically the same issue as in tests/various/plugin.sh, which uses yosys-config to compile a plugin. `yosys-config --cxxflags` points to `$PREFIX/share/` (/usr/local/share by default), which might not exist yet or might be out of date. Building directly from the headers in ./share/ avoids this.
* | | | | | Add codeowners file (#2098)N. Engelhardt2020-06-041-0/+37
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* | | | | | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-046-55/+143
|\ \ \ \ \ \ | |_|_|_|/ / |/| | | | | abc9: -dff improvements
| * | | | | abc9_ops: fix commentEddie Hung2020-05-301-1/+1
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| * | | | | abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-302-8/+8
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| * | | | | abc9_ops: optimise to not derive unless attribute existsEddie Hung2020-05-291-4/+8
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| * | | | | abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-293-7/+25
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| * | | | | tests: add test for abc9 -dff removing a redundant flop entirelyEddie Hung2020-05-251-0/+15
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| * | | | | abc9_ops: -reintegrate to preserve flop namesEddie Hung2020-05-251-5/+25
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| * | | | | tests: add testcase for abc9 -dff preserving flop namesEddie Hung2020-05-251-0/+34
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| * | | | | aiger: cleanupEddie Hung2020-05-251-2/+5
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| * | | | | xaiger: cleanupEddie Hung2020-05-251-28/+22
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* | | | | | Add printf format attributes to btorf/infof helper functionsClaire Wolf2020-06-041-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | | | Merge pull request #2108 from nakengelhardt/btor_internal_namesclairexen2020-06-041-33/+42
|\ \ \ \ \ \ | | | | | | | | | | | | | | btor backend: add option to not include internal names
| * | | | | | btor backend: add option to not include internal namesN. Engelhardt2020-06-041-33/+42
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* | | | | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-047-2/+19
|\ \ \ \ \ \ | | | | | | | | | | | | | | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | | | | | frontends/json/jsonparse.cc: Like the upto field read_json can also read the ↵Vamsi K Vytla2020-04-271-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | signedness of a wire
| * | | | | | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-276-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | | | | | Merge pull request #2070 from hackfin/masterN. Engelhardt2020-06-042-13/+16
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Pyosys API: idict type handling
| * \ \ \ \ \ \ Merge branch 'master' of https://github.com/hackfin/yosysMartin2020-05-191-7/+36
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| * | | | | | | | idict handling in wrapperMartin2020-05-192-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Also, re-applied no-line-break workaround to rtlil.h to make parser catch all methods.
* | | | | | | | | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-033-3/+18
|\ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|/ / |/| | | | | | | | abc9: fixes around handling combinatorial loops
| * | | | | | | | tests: tidy up testcaseEddie Hung2020-06-031-3/+0
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| * | | | | | | | abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposortEddie Hung2020-05-251-2/+4
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