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* Merge pull request #1310 from SergeyDegtyar/masterEddie Hung2019-08-3037-1/+766
|\ | | | | Add new tests for ice40 architecture
| * macc test fixSergeyDegtyar2019-08-301-1/+1
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| * Fix macc testSergeyDegtyar2019-08-301-1/+1
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| * div_mod test fixSergeyDegtyar2019-08-301-1/+1
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| * fix div_mod testSergeyDegtyar2019-08-301-1/+1
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| * Fix test for counterSergeyDegtyar2019-08-301-1/+1
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| * Merge branch 'master' into masterSergey2019-08-306-27/+51
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| * | Add new tests.SergeyDegtyar2019-08-3010-0/+200
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| * | Remove unnecessary common.v(assertions for testbenches).SergeyDegtyar2019-08-301-47/+0
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| * | Remove simulation from run-test.sh (unnecessary paths)SergeyDegtyar2019-08-301-16/+9
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| * | Remove simulation from run-test.shSergeyDegtyar2019-08-301-6/+0
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| * | Merge pull request #2 from YosysHQ/masterSergey2019-08-2910-127/+341
| |\ \ | | | | | | | | Pull from upstream
| * \ \ Merge pull request #3 from YosysHQ/Sergey/tests_ice40Sergey2019-08-2974-820/+3636
| |\ \ \ | | | | | | | | | | Merge my changes to tests_ice40 branch
| | * | | Comment out *.sh used for testbenches as we have no moreEddie Hung2019-08-281-8/+8
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| | * | | Use equiv for memory and dpramEddie Hung2019-08-284-168/+2
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| | * | | Use equiv_opt for latchesEddie Hung2019-08-282-58/+10
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| | * | | Merge remote-tracking branch 'origin/clifford/async2synclatch' into ↵Eddie Hung2019-08-2867-586/+3616
| | |\ \ \ | | | | | | | | | | | | | | | | | | Sergey/tests_ice40
| * | | | | Add comments for examples from Lattice user guideSergeyDegtyar2019-08-293-0/+9
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| * | | | Revert "Add tests for ecp5"SergeyDegtyar2019-08-2831-863/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit 2270ead09fb4695442c66fe5c06445235f390f2b.
| * | | | Add tests for ecp5SergeyDegtyar2019-08-2831-0/+863
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| * | | | Revert "Add tests for ecp5 architecture."SergeyDegtyar2019-08-2731-865/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit 134d3fea909bae02f4f814e3d649658502b44b73.
| * | | | Add tests for ecp5 architecture.SergeyDegtyar2019-08-2731-0/+865
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| * | | | Add tests for macc and rom;SergeyDegtyar2019-08-274-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Test cases from https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071; In both cases synthesized only LUTs and DFFs.
| * | | | Fix pull requestSergeyDegtyar2019-08-232-7/+9
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| * | | | Fix run-test.sh; Add new test for dpram.SergeyDegtyar2019-08-234-1/+120
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| * | | | Fix path in run-test.shSergeyDegtyar2019-08-231-3/+3
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| * | | | Merge pull request #1 from YosysHQ/Sergey/tests_ice40Sergey2019-08-2318-138/+91
| |\ \ \ \ | | | | | | | | | | | | tests_ice40 improvements
| | * | | | Remove adffs_tb.vEddie Hung2019-08-221-75/+0
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| | * | | | WIP for equivalency checking memoriesEddie Hung2019-08-221-1/+13
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| | * | | | Do not print OKAYEddie Hung2019-08-222-4/+0
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| | * | | | SpellingEddie Hung2019-08-221-2/+2
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| | * | | | Fail if iverilog failsEddie Hung2019-08-221-2/+2
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| | * | | | Hide tri-state warning message for nowEddie Hung2019-08-222-1/+2
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| | * | | | Remove unused outputEddie Hung2019-08-221-1/+1
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| | * | | | Fix tribuf testEddie Hung2019-08-221-1/+1
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| | * | | | Fix commentsEddie Hung2019-08-228-10/+11
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| | * | | | Remove tech independent synthesisEddie Hung2019-08-229-16/+20
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| | * | | | Remove dffe instantationEddie Hung2019-08-221-7/+0
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| | * | | | Move $dffe to dffs.{v,ys}Eddie Hung2019-08-224-18/+41
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| | * | | | Make multiplier wider, do not do tech independent synthEddie Hung2019-08-222-8/+6
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| * | | | Fix all comments from PRSergeyDegtyar2019-08-2120-160/+465
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| * | | | Add temp directorySergeyDegtyar2019-08-211-0/+1
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| * | | | Fix tests; Remove simulation;SergeyDegtyar2019-08-2026-519/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add -map and -assert options for equiv_opt; !!! '-assert' option was commented for the next tests (unproven $equiv cells was found): - dffs; - div_mod; - latches; - mul_pow; - Add design -load; - Remove simulations;
| * | | | Add new tests for ice40 architectureSergeyDegtyar2019-08-2028-0/+901
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* | | | | Merge pull request #1321 from YosysHQ/eddie/xilinx_srlEddie Hung2019-08-3013-224/+816
|\ \ \ \ \ | | | | | | | | | | | | xilinx_srl pass for shift register extraction
| * \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-3018-139/+264
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| * | | | | | CleanupEddie Hung2019-08-281-4/+0
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| * | | | | | Account for D port being a constantEddie Hung2019-08-281-4/+4
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| * | | | | | No need to replace Q of slice since $shiftx is autoremove-dEddie Hung2019-08-281-1/+0
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| * | | | | | More cleanupEddie Hung2019-08-281-12/+14
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