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* Ignoring more system task and functionsClifford Wolf2015-01-152-2/+4
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* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
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* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
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* Various cleanups in synth_xilinx commandClifford Wolf2015-01-131-54/+8
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* Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)Clifford Wolf2015-01-131-5/+0
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* Tiny fix in vcdcd.plClifford Wolf2015-01-131-2/+2
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* Small Makefile typo fixClifford Wolf2015-01-131-2/+2
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* Only enable code coverage counters on linuxClifford Wolf2015-01-094-6/+6
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* Merge pull request #46 from utzig/masterClifford Wolf2015-01-083-5/+11
|\ | | | | Fixes building on a Mac using Homebrew as package manager
| * Enable use of homebrew's provided bison if availableFabio Utzig2015-01-081-0/+2
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| * Enable bison to be customizedFabio Utzig2015-01-083-2/+3
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| * Add homebrew's libffi pathsFabio Utzig2015-01-081-0/+3
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| * Add homebrew's readline pathsFabio Utzig2015-01-081-3/+3
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* Added add_share_file Makefile macroClifford Wolf2015-01-083-38/+17
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* added minimalistic xilinx sim modelsClifford Wolf2015-01-081-0/+150
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* disabled problematic mux -> and/or transformClifford Wolf2015-01-071-2/+7
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* More Xilinx bram cleanupsClifford Wolf2015-01-071-14/+14
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* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-072-36/+36
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* memory_bram hotfix for memories with width 1Clifford Wolf2015-01-061-3/+3
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* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-063-16/+320
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* Towards Xilinx bram supportClifford Wolf2015-01-063-24/+65
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* small fix in xilinx/brams.vClifford Wolf2015-01-061-5/+5
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* fixed compiler warning on non-linux archsClifford Wolf2015-01-061-2/+4
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* removed old debug codeClifford Wolf2015-01-061-1/+0
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* hashlib iterator fixClifford Wolf2015-01-061-4/+4
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* build fix for mxeClifford Wolf2015-01-061-7/+8
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* Towards Xilinx bram supportClifford Wolf2015-01-065-26/+176
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* Various small improvements to synth_xilinxClifford Wolf2015-01-062-10/+8
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* Towards Xilinx bram supportClifford Wolf2015-01-063-14/+42
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* Towards Xilinx bram supportClifford Wolf2015-01-063-6/+10
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* dict<> ref vs insert bugfixClifford Wolf2015-01-061-10/+13
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* Towards Xilinx bram supportClifford Wolf2015-01-058-19/+175
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* Towards Xilinx bram supportClifford Wolf2015-01-044-16/+186
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* Added memory_bram "shuffle_enable" featureClifford Wolf2015-01-042-1/+117
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* Removed left over debug code from memory_bramClifford Wolf2015-01-041-2/+2
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* Fixed pattern matching in "hierarchy -generate"Clifford Wolf2015-01-041-2/+2
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* Print non-errors to stdoutClifford Wolf2015-01-033-2/+11
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* Added "memory -bram"Clifford Wolf2015-01-032-3/+12
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* Added memory_bram 'or_next_if_better' featureClifford Wolf2015-01-032-45/+162
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* memory_bram transp supportClifford Wolf2015-01-032-46/+88
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* Progress in memory_bramClifford Wolf2015-01-035-25/+25
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* Cosmetic changes in verilog output formatClifford Wolf2015-01-021-5/+10
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* Added proper clkpol support to memory_bramClifford Wolf2015-01-023-6/+34
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* Fixes and improvements in bram testClifford Wolf2015-01-021-20/+8
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* Progress in bram testbenchClifford Wolf2015-01-021-11/+28
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* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-021-1/+2
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* New $mem simlib modelClifford Wolf2015-01-021-95/+36
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* Progress in memory_bramClifford Wolf2015-01-025-16/+18
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* Progress in memory_bramClifford Wolf2015-01-024-23/+42
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* Progress in bram testbenchClifford Wolf2015-01-013-42/+184
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