iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add examples/osu035	Clifford Wolf	2017-05-23	4	-0/+30
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2017-05-23	1	-17/+70
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\| *	Merge pull request #346 from azonenberg/master	Clifford Wolf	2017-05-23	1	-17/+70
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\| \| *	greenpak4_counters: Added support for parallel output from GP_COUNTx cells	Andrew Zonenberg	2017-05-22	1	-17/+70
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* /	Add workaround for CBMC bug to SimpleC back-end	Clifford Wolf	2017-05-17	1	-1/+3
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*	Enable readline and tcl in mxe builds	Clifford Wolf	2017-05-17	3	-4/+44
*	Add missing AndnotGate() and OrnotGate() declarations to rtlil.h	Clifford Wolf	2017-05-17	1	-13/+15
*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	14	-91/+211
*	Add <modname>_init() function generator to simpleC back-end	Clifford Wolf	2017-05-16	2	-88/+152
*	Improve simplec back-end	Clifford Wolf	2017-05-16	1	-1/+1
*	Improve simplec back-end	Clifford Wolf	2017-05-15	1	-42/+44
*	Improve simplec back-end	Clifford Wolf	2017-05-14	3	-3/+49
*	Improve simplec back-end	Clifford Wolf	2017-05-13	1	-25/+60
*	Improve simplec back-end	Clifford Wolf	2017-05-12	3	-12/+78
*	Added support for more gate types to simplec back-end	Clifford Wolf	2017-05-12	1	-1/+88
*	Add first draft of simple C back-end	Clifford Wolf	2017-05-12	6	-0/+623
*	Update ABC to hg rev e79576e10d72	Clifford Wolf	2017-05-11	1	-1/+1
*	Fix boolector support in yosys-smtbmc	Clifford Wolf	2017-05-08	1	-18/+18
*	Add support for localparam in module header	Clifford Wolf	2017-04-30	1	-1/+7
*	Fix equiv_simple, old behavior now available with "equiv_simple -short"	Clifford Wolf	2017-04-28	1	-10/+41
*	Add support for `resetall compiler directive	Clifford Wolf	2017-04-26	1	-0/+7
*	Replace CRLF line endings with LF in de2i.qsf (quartus example)	Clifford Wolf	2017-04-12	1	-1098/+1098
*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	19	-165/+165
*	Add MAX10 and Cyclone IV items to CHANGELOG	Clifford Wolf	2017-04-07	1	-0/+13
*	Merge pull request #337 from dh73/master	Clifford Wolf	2017-04-07	25	-0/+2255
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\| *	Add initial support for both MAX10 and Cyclone IV (E\|GX) FPGAs	dh73	2017-04-05	25	-0/+2255
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*	Add ConstEval defaultval feature	Clifford Wolf	2017-04-05	1	-1/+8
*	Fix gcc compiler warning	Clifford Wolf	2017-04-05	1	-1/+1
*	Add front-end detection for *.tcl files	Clifford Wolf	2017-03-28	1	-1/+6
*	Add minisat 00_PATCH_typofixes.patch	Clifford Wolf	2017-03-27	2	-0/+21
*	Remove use of <fpu_control.h> in minisat	Clifford Wolf	2017-03-27	4	-18/+44
*	Add "write_smt2 -stdt" mode	Clifford Wolf	2017-03-20	2	-37/+84
*	Add generation of logic cells to EDIF back-end runtest.py	Clifford Wolf	2017-03-19	1	-2/+6
*	Fix EDIF: portRef member 0 is always the MSB bit	Clifford Wolf	2017-03-19	2	-13/+14
*	Add simple EDIF test case generator and checker	Clifford Wolf	2017-03-18	1	-0/+113
*	Fix verilog pre-processor for multi-level relative includes	Clifford Wolf	2017-03-14	1	-4/+26
*	Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg	Clifford Wolf	2017-03-04	2	-33/+87
*	Add write_aiger $anyseq support	Clifford Wolf	2017-03-02	1	-0/+7
*	Allow $anyconst, etc. in non-formal SV mode	Clifford Wolf	2017-03-01	1	-1/+1
*	Disable opt_merge for $anyseq and $anyconst	Clifford Wolf	2017-02-28	1	-0/+3
*	Use hex addresses in smtbmc vcd mem traces	Clifford Wolf	2017-02-28	1	-1/+1
*	Add "chformal -assert2assume" and friends	Clifford Wolf	2017-02-28	1	-0/+44
*	Add "chformal" pass	Clifford Wolf	2017-02-27	2	-0/+239
*	Add smtbmc support for memory vcd dumping	Clifford Wolf	2017-02-26	1	-0/+98
*	Fix extra newline bug in write_smt2	Clifford Wolf	2017-02-26	1	-1/+1
*	Fix bug in smtio unroll code	Clifford Wolf	2017-02-26	1	-3/+2
*	Fix assert checking in "yosys-smtbmc -c --append"	Clifford Wolf	2017-02-26	1	-1/+1
*	Improve (and fix for stbv mode) SMT2 memory API	Clifford Wolf	2017-02-26	3	-47/+51
*	Add support for "yosys-smtbmc -c --append"	Clifford Wolf	2017-02-25	1	-1/+13
*	Update ABC to hg rev 3a95bfa55df7	Clifford Wolf	2017-02-25	1	-1/+1