| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Improve "verific -all" handling | Clifford Wolf | 2017-07-25 | 1 | -26/+45 |
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| * | Add "verific -import -d <dump_file" | Clifford Wolf | 2017-07-24 | 1 | -6/+35 |
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| * | Add "verific -import -flatten" and "verific -import -v" | Clifford Wolf | 2017-07-24 | 1 | -107/+164 |
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| * | Add more SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 5 | -1/+74 |
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| * | Add "verific -import -k" | Clifford Wolf | 2017-07-22 | 1 | -42/+51 |
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| * | Add error for cell output ports that are connected to constants | Clifford Wolf | 2017-07-22 | 1 | -20/+21 |
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| * | Add some simple SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 4 | -0/+45 |
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| * | Improve docs for verific bindings, add simply sby example | Clifford Wolf | 2017-07-22 | 5 | -48/+89 |
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| * | Fix handling of empty cell port assignments (i.e. ignore them) | Clifford Wolf | 2017-07-21 | 2 | -0/+6 |
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| * | Fix "read_blif -wideports" handling of cells with wide ports | Clifford Wolf | 2017-07-21 | 1 | -3/+33 |
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| * | Add a paragraph about pre-defined macros to read_verilog help message | Clifford Wolf | 2017-07-21 | 1 | -0/+4 |
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| * | Add verilator support to testbenches generated by yosys-smtbmc | Clifford Wolf | 2017-07-21 | 1 | -3/+15 |
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| * | Change intptr_t to uintptr_t in hashlib.h | Clifford Wolf | 2017-07-18 | 1 | -1/+1 |
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| * | Merge pull request #363 from rqou/master | Clifford Wolf | 2017-07-18 | 2 | -1/+6 |
| |\ | | | | | Miscellaneous build tweaks | ||||
| | * | makefile: Add the option to use libtermcap | Robert Ou | 2017-07-17 | 1 | -0/+5 |
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| | * | Fix build warnings for win64 | Robert Ou | 2017-07-17 | 1 | -1/+1 |
| |/ | | | | Win64 has a 32-bit long. Use intptr_t to work on any data model. | ||||
| * | Add $alu to list of supported cells for "stat -width" | Clifford Wolf | 2017-07-14 | 1 | -1/+1 |
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| * | Generate FSM-style testbenches in smtbmc | Clifford Wolf | 2017-07-12 | 1 | -5/+23 |
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| * | Fix the fixed handling of x-bits in EDIF back-end | Clifford Wolf | 2017-07-11 | 1 | -1/+0 |
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| * | Fix handling of x-bits in EDIF back-end | Clifford Wolf | 2017-07-11 | 1 | -1/+11 |
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| * | Add attributes and parameter support to JSON front-end | Clifford Wolf | 2017-07-10 | 2 | -7/+52 |
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| * | Add techlibs/xilinx/lut2lut.v | Clifford Wolf | 2017-07-10 | 2 | -0/+66 |
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| * | Add JSON front-end | Clifford Wolf | 2017-07-08 | 2 | -0/+472 |
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| * | Change s/asserts/assertions/ in yosys-smtbmc log messages | Clifford Wolf | 2017-07-07 | 1 | -2/+2 |
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| * | Add "yosys-smtbmc --presat" | Clifford Wolf | 2017-07-07 | 1 | -3/+23 |
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| * | Fix generation of multiple outputs for same AIG node in write_aiger | Clifford Wolf | 2017-07-05 | 1 | -13/+30 |
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| * | Add write_table command | Clifford Wolf | 2017-07-05 | 2 | -0/+123 |
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| * | Add Verific Release information to log | Clifford Wolf | 2017-07-04 | 1 | -0/+12 |
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| * | Fix some c++ clang compiler errors | Clifford Wolf | 2017-07-03 | 1 | -3/+3 |
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| * | Apply minor coding style changes to coolrunner2 target | Clifford Wolf | 2017-07-03 | 2 | -1/+1 |
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| * | Merge pull request #352 from rqou/master | Clifford Wolf | 2017-07-03 | 6 | -0/+645 |
| |\ | | | | | Initial Coolrunner-II support | ||||
| | * | coolrunner2: Add a few more primitives | Robert Ou | 2017-06-25 | 1 | -0/+110 |
| | | | | | | | | | These cannot be inferred yet, but add them to cells_sim.v for now | ||||
| | * | coolrunner2: Initial mapping of latches | Robert Ou | 2017-06-25 | 4 | -0/+63 |
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| | * | coolrunner2: Initial mapping of DFFs | Robert Ou | 2017-06-25 | 4 | -0/+76 |
| | | | | | | | | | | | All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered) | ||||
| | * | coolrunner2: Remove redundant INVERT_PTC | Robert Ou | 2017-06-25 | 2 | -4/+1 |
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| | * | coolrunner2: Remove debug prints | Robert Ou | 2017-06-25 | 1 | -2/+0 |
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| | * | coolrunner2: Correctly handle $_NOT_ after $sop | Robert Ou | 2017-06-25 | 1 | -5/+41 |
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| | * | coolrunner2: Also construct the XOR cell in the macrocell | Robert Ou | 2017-06-25 | 2 | -7/+34 |
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| | * | coolrunner2: Initial techmapping for $sop | Robert Ou | 2017-06-25 | 4 | -153/+268 |
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| | * | coolrunner2: Initial commit | Robert Ou | 2017-06-24 | 3 | -0/+223 |
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| * | | Merge pull request #356 from set-soft/clean-test | Clifford Wolf | 2017-07-03 | 1 | -0/+8 |
| |\ \ | | | | | | | Added the test outputs to the clean target | ||||
| | * | | Added the test outputs to the clean target | Salvador E. Tropea | 2017-07-03 | 1 | -0/+8 |
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| * | | | Merge pull request #355 from set-soft/exclude_TBUF_merge | Clifford Wolf | 2017-07-03 | 1 | -0/+1 |
| |\ \ \ | |/ / |/| | | Excluded $_TBUF_ from opt_merge pass | ||||
| | * | | Excluded $_TBUF_ from opt_merge pass | Salvador E. Tropea | 2017-07-03 | 1 | -0/+1 |
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| * | | Remove unneeded delays in smtbmc vlogtb | Clifford Wolf | 2017-07-03 | 1 | -1/+1 |
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| * | | Include output ports with constant driver in AIGER output | Clifford Wolf | 2017-07-03 | 1 | -2/+18 |
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| * | | Add "yosys-smtbmc --vlogtb-top" | Clifford Wolf | 2017-07-01 | 1 | -15/+32 |
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| * | | Fix and_or_buffer optimization in opt_expr for signed operators | Clifford Wolf | 2017-07-01 | 1 | -2/+2 |
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| * | | Fix smtbmc vlogtb bug in $anyseq handling | Clifford Wolf | 2017-07-01 | 1 | -3/+3 |
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| * | | Add "design -import" | Clifford Wolf | 2017-06-30 | 1 | -3/+94 |
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