| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | greenpak4: add GP_COUNT{8,14}_ADV cells. | whitequark | 2016-07-10 | 1 | -0/+26 |
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| * | Further improved fsm_detect output, attempt to detect self-resetting circuits | Clifford Wolf | 2016-07-09 | 1 | -6/+68 |
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| * | Added printing of some warning messages to fsm_detect | Clifford Wolf | 2016-07-09 | 1 | -14/+61 |
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| * | Added warning about adding fsm_encoding attributes to wires to manual | Clifford Wolf | 2016-07-08 | 1 | -0/+4 |
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| * | Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations | Clifford Wolf | 2016-07-08 | 2 | -13/+24 |
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| * | Fixed mem assignment in left-hand-side concatenation | Clifford Wolf | 2016-07-08 | 2 | -0/+57 |
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| * | Merge branch 'eddiehung-vtr' | Clifford Wolf | 2016-07-08 | 1 | -9/+17 |
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| | * | Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior | Clifford Wolf | 2016-07-08 | 1 | -13/+15 |
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| | * | In BLIF, a .names without entries already always outputs 0 | Clifford Wolf | 2016-07-08 | 1 | -11/+0 |
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| | * | Undo eddiehung-vtr Makefile changes | Clifford Wolf | 2016-07-08 | 1 | -5/+1 |
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| | * | Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into ↵ | Clifford Wolf | 2016-07-08 | 2 | -3/+24 |
| |/| | | | | | | | eddiehung-vtr | ||||
| | * | Fix for all zero mask | eddiehung | 2015-05-03 | 2 | -1/+16 |
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| | * | Escape '<' and '>' some more | eddiehung | 2015-05-03 | 1 | -1/+1 |
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| | * | For vtr, escape angle brackets as well | eddiehung | 2015-04-28 | 1 | -1/+1 |
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| | * | blifwriter: write out .names for true/false/undef type == '-' | eddiehung | 2015-04-28 | 1 | -0/+6 |
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| * | | Fixed autotest.sh handling of `timescale | Clifford Wolf | 2016-07-02 | 1 | -14/+10 |
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| * | | Merge branch 'assert-limit' | Clifford Wolf | 2016-07-01 | 1 | -9/+33 |
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| | * | | Replaced "select -assert-limit" with -assert-max and -assert-min | Clifford Wolf | 2016-07-01 | 1 | -42/+29 |
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| | * | | Added 'assert-limit' option for 'select' command | eshellko | 2016-07-01 | 1 | -5/+42 |
| |/ / | | | | | For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done. | ||||
| * | | Improved ice40_ffinit error reporting | Clifford Wolf | 2016-06-30 | 1 | -1/+5 |
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| * | | Merge pull request #181 from rubund/input_logic_allowed | Clifford Wolf | 2016-06-21 | 1 | -2/+2 |
| |\ \ | | | | | | | Allow defining input ports as "input logic" in SystemVerilog | ||||
| | * | | Allow defining input ports as "input logic" in SystemVerilog | Ruben Undheim | 2016-06-20 | 1 | -2/+2 |
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| * | | Bugfix in "abc -script" handling | Clifford Wolf | 2016-06-19 | 1 | -53/+50 |
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| * | | Merge branch 'sv_packages' of https://github.com/rubund/yosys | Clifford Wolf | 2016-06-19 | 7 | -1/+52 |
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| | * | | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 3 | -5/+4 |
| | | | | | | | | | | | | | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h | ||||
| | * | | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 7 | -1/+53 |
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| * | | | Added "deminout" | Clifford Wolf | 2016-06-19 | 3 | -0/+118 |
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| * | | | Added "read_blif -sop" | Clifford Wolf | 2016-06-18 | 1 | -5/+10 |
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| * | | | Added $sop support to BLIF back-end | Clifford Wolf | 2016-06-18 | 1 | -2/+29 |
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| * | | Added "dc2" to default ABC scripts | Clifford Wolf | 2016-06-17 | 1 | -5/+5 |
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| * | | Fixed init issue in mem2reg_test2 test case | Clifford Wolf | 2016-06-17 | 1 | -2/+6 |
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| * | | Added "abc -I <num> -P <num>" | Clifford Wolf | 2016-06-17 | 1 | -8/+33 |
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| * | | Added $sop SAT model | Clifford Wolf | 2016-06-17 | 1 | -0/+82 |
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| * | | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 6 | -10/+89 |
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| * | | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 7 | -31/+171 |
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| * | | Updated ABC to hg rev b5df6e2b76f0 | Clifford Wolf | 2016-06-17 | 2 | -10/+10 |
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| * | | Added "nlutmap -assert" | Clifford Wolf | 2016-06-09 | 2 | -3/+17 |
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| * | | Do not run "wreduce" in "prep -ifx" | Clifford Wolf | 2016-06-08 | 1 | -2/+3 |
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| * | | Added "proc_mux -ifx" | Clifford Wolf | 2016-06-06 | 3 | -21/+54 |
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| * | | Added "setundef -init" | Clifford Wolf | 2016-06-03 | 1 | -5/+89 |
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| * | | Fix all undef-muxes in dlatch input cone | Clifford Wolf | 2016-06-02 | 1 | -34/+72 |
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| * | | Avoid creating undef-muxes when inferring latches in proc_dlatch | Clifford Wolf | 2016-06-01 | 1 | -0/+44 |
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| * | | Added opt_expr support for div/mod by power-of-two | Clifford Wolf | 2016-05-29 | 2 | -0/+96 |
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| * | | Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} | Clifford Wolf | 2016-05-27 | 1 | -0/+11 |
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| * | | Fixed access-after-delete bug in mem2reg code | Clifford Wolf | 2016-05-27 | 2 | -6/+23 |
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| * | | fixed typos in error messages | Clifford Wolf | 2016-05-27 | 1 | -3/+3 |
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| * | | Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop | Clifford Wolf | 2016-05-27 | 1 | -3/+3 |
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| * | | Merge pull request #172 from zeldin/deterministic_hierarchy | Clifford Wolf | 2016-05-22 | 1 | -3/+3 |
| |\ \ | | | | | | | Made the expansion order of hierarchy deterministic | ||||
| | * | | Made the expansion order of hierarchy deterministic | Marcus Comstedt | 2016-05-22 | 1 | -3/+3 |
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| * | | Some fixes in tests/asicworld/*_tb.v | Clifford Wolf | 2016-05-20 | 4 | -50/+41 |
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