| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Merge branch 'master' of https://github.com/Kmanfi/yosys | Clifford Wolf | 2016-05-20 | 2 | -11/+18 | |
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| | * | | Close opened dump file. | Kaj Tuomi | 2016-05-19 | 1 | -0/+1 | |
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| | * | | Fix for Modelsim transcript line warp issue #164 | Kaj Tuomi | 2016-05-19 | 2 | -11/+17 | |
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| * | | | Also escape "=" in spice output | Clifford Wolf | 2016-05-20 | 1 | -1/+1 | |
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| * | | | Small improvements in Verilog front-end docs | Clifford Wolf | 2016-05-20 | 2 | -0/+8 | |
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| * | | Don't sign-extend memory bram initialization data | Clifford Wolf | 2016-05-15 | 1 | -1/+1 | |
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| * | | Added missing "#define HASHLIB_H" | Clifford Wolf | 2016-05-14 | 1 | -0/+1 | |
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| * | | Minor presentation fixes | Clifford Wolf | 2016-05-14 | 1 | -1/+1 | |
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| * | | Updated min GCC requirement to GCC 4.8 | Clifford Wolf | 2016-05-11 | 2 | -14/+14 | |
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| * | | Added manual download link to README | Clifford Wolf | 2016-05-09 | 1 | -0/+4 | |
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| * | | Include <cmath> in yosys.h | Clifford Wolf | 2016-05-08 | 2 | -9/+1 | |
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| * | | Merge pull request #162 from azonenberg/master | Clifford Wolf | 2016-05-08 | 1 | -2/+33 | |
| |\ \ | | | | | | | Added GP_DELAY cell. Fixed several errors in simulation models. | |||||
| | * | | Added GP_DELAY cell | Andrew Zonenberg | 2016-05-07 | 1 | -0/+29 | |
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| | * | | Fixed typo in port name | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
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| | * | | Fixed extra semicolon | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
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| | * | | Fixed typo in parameter name | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
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| | * | | Added simulation timescale declaration | Andrew Zonenberg | 2016-05-07 | 1 | -0/+2 | |
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| * | | Fixes for MXE build | Clifford Wolf | 2016-05-07 | 3 | -10/+10 | |
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| * | | Added support for "keep" attribute to shregmap | Clifford Wolf | 2016-05-07 | 1 | -2/+2 | |
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| * | | Added synth_ice40 support for latches via logic loops | Clifford Wolf | 2016-05-06 | 3 | -0/+13 | |
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| * | | Added "write_blif -noalias" | Clifford Wolf | 2016-05-06 | 1 | -6/+26 | |
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| * | | Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" | Clifford Wolf | 2016-05-06 | 1 | -3/+15 | |
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| * | | Fixed preservation of important attributes in techmap | Clifford Wolf | 2016-05-06 | 1 | -4/+32 | |
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| * | | Merge pull request #159 from azonenberg/master | Clifford Wolf | 2016-05-05 | 5 | -24/+7 | |
| |\ \ | | | | | | | Fixes to use new I/O pad techmapping, renamed ports for GP_SHREG | |||||
| | * | | Changed order of passes for better handling of INIT attributes on "output ↵ | Andrew Zonenberg | 2016-05-04 | 1 | -2/+2 | |
| | | | | | | | | | | | | | reg" FFs | |||||
| | * | | Changed port names in greenpak shregmap | Andrew Zonenberg | 2016-05-04 | 1 | -1/+1 | |
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| | * | | Renamed module parameter | Andrew Zonenberg | 2016-05-04 | 1 | -4/+4 | |
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| | * | | Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT ↵ | Andrew Zonenberg | 2016-05-04 | 3 | -18/+1 | |
| |/ / | | | | | | | cells instead of extract | |||||
| * | | Added tristate buffer support to iopadmap | Clifford Wolf | 2016-05-04 | 1 | -4/+161 | |
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| * | | Merge pull request #157 from azonenberg/master | Clifford Wolf | 2016-05-04 | 5 | -0/+52 | |
| |\ \ | | | | | | | Added GP_ABUF cell, support for tri-state I/O buffers in GreenPak | |||||
| | * | | Fixed incorrect signal naming in GP_IOBUF | Andrew Zonenberg | 2016-05-04 | 1 | -2/+2 | |
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| | * | | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-05-04 | 1 | -0/+1 | |
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| * | | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-05-04 | 1 | -0/+11 | |
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| * | | | | Fixed iopadmap attribute handling | Clifford Wolf | 2016-05-04 | 1 | -0/+1 | |
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| | | * | | Added tri-state I/O extraction for GreenPak | Andrew Zonenberg | 2016-05-03 | 5 | -2/+29 | |
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| | | * | | Added GreenPak I/O buffer cells | Andrew Zonenberg | 2016-05-03 | 1 | -0/+17 | |
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| | | * | | Added comment to clarify GP_ABUF cell | Andrew Zonenberg | 2016-05-02 | 1 | -0/+2 | |
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| | | * | | Added GP_ABUF cell | Andrew Zonenberg | 2016-05-02 | 1 | -0/+6 | |
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| | * | | Merge pull request #154 from azonenberg/master | Clifford Wolf | 2016-05-02 | 1 | -0/+11 | |
| |/| | | | | | | | | Add GP_PGA cell | |||||
| | * | | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-05-01 | 1 | -1/+1 | |
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| * | | | Improved TCL_VERSION detection so it does not read .tclshrc | Clifford Wolf | 2016-04-29 | 1 | -1/+1 | |
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| | * | | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-29 | 1 | -0/+30 | |
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| * | | | Added "qwp -v" | Clifford Wolf | 2016-04-28 | 1 | -0/+30 | |
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| | * | | Added GP_PGA cell | Andrew Zonenberg | 2016-04-27 | 1 | -0/+11 | |
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| * | | Connections between inputs and inouts are driven by the input | Clifford Wolf | 2016-04-26 | 1 | -0/+3 | |
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| * | | Fixed test_autotb for modules with many cell ports | Clifford Wolf | 2016-04-25 | 1 | -3/+6 | |
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| * | | Fixed proc_mux performance bug | Clifford Wolf | 2016-04-25 | 1 | -0/+3 | |
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| * | | Merge pull request #150 from azonenberg/master | Clifford Wolf | 2016-04-25 | 1 | -0/+13 | |
| |\ \ | | | | | | | GreenPak analog comparator support | |||||
| | * \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-24 | 6 | -72/+163 | |
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| * | | | Fixed performance bug in proc_dlatch | Clifford Wolf | 2016-04-24 | 1 | -2/+61 | |
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index : iCE40/yosys | |
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