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* Completed ngspice digital example with verilog tbUros Platise2016-03-055-9/+76
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* Added digital (xspice) example code to examples/cmos/Clifford Wolf2016-03-024-1/+70
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* Be more conservative with net names in spice outputClifford Wolf2016-03-021-18/+47
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* Merge pull request #119 from SebKuzminsky/spelling-fixesClifford Wolf2016-02-292-6/+6
|\ | | | | user-facing spelling fixes
| * user-facing spelling fixesSebastian Kuzminsky2016-02-282-6/+6
|/ | | | | "speciefied" -> "specified" "unkown" -> "unknown"
* We are now in 0.6+ developmentClifford Wolf2016-02-261-1/+1
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* Yosys 0.6Clifford Wolf2016-02-261-1/+1
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* Fixed BLIF parser for empty port assignmentsClifford Wolf2016-02-241-2/+2
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* Use easyer-to-read unoptimized ceil_log2()Clifford Wolf2016-02-151-18/+5
| | | | | see here for details on the optimized version: http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
* Updated ABC to ae7d65e71adcClifford Wolf2016-02-151-1/+1
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* Updated command reference in manualClifford Wolf2016-02-143-16/+364
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* Changelog for upcoming 0.6 releaseClifford Wolf2016-02-141-0/+88
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* Fixed more visual studio warningsClifford Wolf2016-02-141-5/+3
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* Fixed some visual studio warningsClifford Wolf2016-02-138-10/+10
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-02-131-1/+1
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| * Fixed MXE ABC buildClifford Wolf2016-02-131-1/+1
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* | Added "int ceil_log2(int)" functionClifford Wolf2016-02-135-10/+58
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* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
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* Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-131-1/+31
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* Updated ABCClifford Wolf2016-02-081-1/+1
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* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
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* Updated ABCClifford Wolf2016-02-071-1/+1
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* Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-041-6/+60
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* Bugfix in Verific front-endClifford Wolf2016-02-031-2/+5
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* Updated verific build instructionsClifford Wolf2016-02-021-2/+0
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* Improved dffsr2dff passClifford Wolf2016-02-021-5/+50
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* Added dffsr2dffClifford Wolf2016-02-023-0/+171
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* Added addBufGate module methodClifford Wolf2016-02-023-0/+8
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* Use alphanumerical order instead of idstring idx in opt_clean compare_signals()Clifford Wolf2016-02-021-1/+1
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* Added CodeOfConductClifford Wolf2016-02-011-0/+73
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* Updated ABC to hg rev ee212a9e94dfClifford Wolf2016-02-011-1/+1
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* Progress in cell library documentationClifford Wolf2016-02-011-0/+238
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* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-012-15/+39
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* Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)Clifford Wolf2016-02-011-8/+68
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* SigMap performance improvementClifford Wolf2016-02-011-1/+7
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* hashlib mfp<> performance improvementsClifford Wolf2016-02-011-2/+7
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* Added reserve() method to haslib classes andClifford Wolf2016-01-311-2/+6
| | | | calculate hashtable size based on entries capacity, not size
* Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosysClifford Wolf2016-01-312-14/+88
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| * rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)Rick Altherr2016-01-311-2/+31
| | | | | | | | | | | | | | | | Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop.
| * rtlil: speed up SigSpec::sort_and_unify()Rick Altherr2016-01-311-1/+11
| | | | | | | | | | | | | | | | | | | | std::set<> internally is often a red-black tree which is fairly expensive to create but fast to lookup. In the case of sort_and_unify(), a set<> is constructed as a temporary object to attempt to speed up lookups. Being a temporarily, however, the cost of creation far outweights the lookup improvement and is a net performance loss. Instead, sort the vector<> that already exists and then apply std::unique().
| * rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)Rick Altherr2016-01-311-6/+14
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| * genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵Rick Altherr2016-01-311-3/+3
| | | | | | | | removeSignalFromCaseTree()
| * rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)Rick Altherr2016-01-311-2/+29
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* | More clang sanitizer stuffClifford Wolf2016-01-312-3/+12
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* Meaningless coding style changeClifford Wolf2016-01-311-1/+0
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* Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosysClifford Wolf2016-01-312-23/+37
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| * rtlil: rewrite remove2() to avoid copyingRick Altherr2016-01-301-45/+18
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| * rtlil: duplicate remove2() for std::set<>Rick Altherr2016-01-292-0/+41
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| * rtlil: change IdString comparison operators to take references instead of copiesRick Altherr2016-01-291-3/+3
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* | Addedd clang sanitizersClifford Wolf2016-01-311-0/+21
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