| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 13 | -4/+53 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Bugfix in hierarchy blackbox module port width handling | Clifford Wolf | 2018-01-07 | 1 | -1/+2 |
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| * | Update ABC to hg rev 6e3c24b3308a | Clifford Wolf | 2018-01-07 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #479 from Fatsie/latch_without_data | Clifford Wolf | 2018-01-05 | 1 | -4/+23 |
| |\ | | | | | Some standard cell libraries include a latch with only set/reset. | ||||
| | * | Some standard cell libraries include a latch with only set/reset. | Staf Verhaegen | 2018-01-03 | 1 | -4/+23 |
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| * | | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 5 | -9/+10 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #480 from Fatsie/liberty_value_expression | Clifford Wolf | 2018-01-04 | 1 | -2/+22 |
| |\ \ | | | | | | | Value of properties can be expression. | ||||
| | * | | Value of properties can be expression. | Staf Verhaegen | 2018-01-03 | 1 | -2/+22 |
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | Example found in the 2007.03 Liberty Reference Manual that was also found in the wild: input_voltage(CMOS) { vil : 0.3 * VDD ; vih : 0.7 * VDD ; vimin : -0.5 ; vimax : VDD + 0.5 ; } Current implementation just parses the expression but no interpretation is done. | ||||
| * / | Temporarily derive blackbox modules in hierarchy to evaluate port widths | Clifford Wolf | 2018-01-04 | 1 | -1/+14 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "no driver for signal bit" error msg to btor back-end | Clifford Wolf | 2017-12-24 | 1 | -0/+2 |
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| * | Bugfix in verilog_defaults argument parser | Clifford Wolf | 2017-12-24 | 1 | -1/+1 |
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| * | Fix minor typo in "prep" help message | Clifford Wolf | 2017-12-19 | 1 | -1/+1 |
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| * | Simple fix BTOR memory encoding | Clifford Wolf | 2017-12-17 | 1 | -2/+2 |
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| * | Improve BTOR memory encoding | Clifford Wolf | 2017-12-17 | 1 | -2/+16 |
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| * | Merge branch 'btor-ng' | Clifford Wolf | 2017-12-15 | 4 | -987/+959 |
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| | * | Add array support to btor back-end | Clifford Wolf | 2017-12-15 | 1 | -6/+169 |
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| | * | Add $anyconst/$anyseq support to btor back-end | Clifford Wolf | 2017-12-15 | 1 | -13/+51 |
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| | * | Merge branch 'master' into btor-ng | Clifford Wolf | 2017-12-14 | 4 | -8/+12 |
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| * | | Add yosys-smtbmc VCD writer support for memories with async writes | Clifford Wolf | 2017-12-14 | 3 | -7/+11 |
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| * | | Fix a bug in clk2fflogic memory handling | Clifford Wolf | 2017-12-14 | 1 | -1/+1 |
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| | * | Merge branch 'master' into btor-ng | Clifford Wolf | 2017-12-14 | 9 | -38/+178 |
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| * | | Add clk2fflogic memory support | Clifford Wolf | 2017-12-14 | 1 | -1/+77 |
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| * | | Add smt2 back-end support for async write memories | Clifford Wolf | 2017-12-14 | 1 | -14/+53 |
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| * | | Add RTLIL::Const::is_fully_ones() | Clifford Wolf | 2017-12-14 | 2 | -0/+12 |
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| * | | Add SigSpec::is_fully_ones() | Clifford Wolf | 2017-12-14 | 2 | -0/+16 |
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| * | | Merge pull request #469 from kkiningh/master | Clifford Wolf | 2017-12-14 | 2 | -2/+2 |
| |\ \ | | | | | | | Use quote includes for yosys.h | ||||
| | * | | Use quote includes for yosys.h | Kevin Kiningham | 2017-12-13 | 2 | -2/+2 |
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| * | | Check for memories in clk2fflogic | Clifford Wolf | 2017-12-13 | 1 | -0/+5 |
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| * | | Merge pull request #468 from grahamedgecombe/fix-sb-io-od | Clifford Wolf | 2017-12-13 | 1 | -19/+19 |
| |\ \ | | | | | | | Fix SB_IO_OD module | ||||
| | * | | Fix port names in SB_IO_OD | Graham Edgecombe | 2017-12-10 | 1 | -18/+18 |
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| | * | | Remove trailing comma from SB_IO_OD port list | Graham Edgecombe | 2017-12-10 | 1 | -1/+1 |
| | | | | | | | | | | | | | This isn't compatible with Icarus Verilog. | ||||
| * | | | Add warnings for driver-driver conflicts between FFs (and other cells) and ↵ | Clifford Wolf | 2017-12-12 | 2 | -3/+11 |
| |/ / | | | | | | | constants | ||||
| | * | Add "write_btor -s" mode | Clifford Wolf | 2017-12-13 | 1 | -6/+50 |
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| | * | Add state initval handling to btor back-end | Clifford Wolf | 2017-12-12 | 1 | -0/+25 |
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| | * | Add btor back-end support for 'x' constants | Clifford Wolf | 2017-12-12 | 1 | -1/+54 |
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| | * | Add SigSpec::is_fully_ones() | Clifford Wolf | 2017-12-12 | 2 | -0/+16 |
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| | * | Add btor $shift/$shiftx support | Clifford Wolf | 2017-12-11 | 2 | -7/+37 |
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| | * | Fix btor back-end shift handling | Clifford Wolf | 2017-12-10 | 2 | -5/+7 |
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| | * | Add support for $pmux in btor back-end | Clifford Wolf | 2017-12-10 | 1 | -0/+23 |
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| | * | Add support for more cell types to btor back-end | Clifford Wolf | 2017-12-10 | 2 | -6/+245 |
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| | * | Merge branch 'master' into btor-ng | Clifford Wolf | 2017-12-10 | 1 | -69/+122 |
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| * | | Add support for Verific PRIM_SVA_NOT properties | Clifford Wolf | 2017-12-10 | 1 | -10/+25 |
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| * | | Add Verific OPER_SVA_STABLE support | Clifford Wolf | 2017-12-10 | 1 | -2/+32 |
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| * | | Refactoring Verific SVA rewriter | Clifford Wolf | 2017-12-10 | 1 | -62/+70 |
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| | * | Fix btor concat | Clifford Wolf | 2017-12-09 | 1 | -1/+1 |
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| | * | Merge branch 'master' into btor-ng | Clifford Wolf | 2017-12-09 | 4 | -4/+9 |
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| * | | Merge pull request #467 from mithro/patch-1 | Clifford Wolf | 2017-12-09 | 1 | -1/+1 |
| |\ \ | | | | | | | Fix spelling in -vpr help for synth_ice40 | ||||
| | * | | Fix spelling in -vpr help for synth_ice40 | Tim Ansell | 2017-12-08 | 1 | -1/+1 |
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| * | | Use "hg ... --insecure" for cloning/pulling ABC | Clifford Wolf | 2017-12-03 | 1 | -2/+2 |
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| * | | Update ABC to hg rev 31fc97b0aeed | Clifford Wolf | 2017-12-02 | 1 | -1/+1 |
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index : iCE40/yosys | |
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